Dismiss
InnovationQ will be updated on Sunday, Oct. 22, from 10am ET - noon. You may experience brief service interruptions during that time.
Browse Prior Art Database

Parallel Random Test Generation

IP.com Disclosure Number: IPCOM000046477D
Original Publication Date: 1983-Jul-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 2 page(s) / 54K

Publishing Venue

IBM

Related People

Hsiao, MY: AUTHOR

Abstract

This apparatus generates multiple tests in parallel.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 100% of the total text.

Page 1 of 2

Parallel Random Test Generation

This apparatus generates multiple tests in parallel.

Latch circuits 12 embodied in semiconductor circuitry 14 are shift register latches (SRLs) formed by a serial path 16 to permit the entry and removal of data in series for testing purposes. These latches can be connected together to form a Y-1 linear feedback shift register (LFSR), as shown in Fig. 2, to generate PN sequences Y of length 2Y-1, illustrated in Fig. 3. PN sequences generated by the LFSR on one chip can be used to generate the PN sequences for an adjacent chip, as shown in Fig. 1.

1

Page 2 of 2

2

[This page contains 4 pictures or other non-text objects]