Browse Prior Art Database

Extended RAM for Virtual Memory Terminal

IP.com Disclosure Number: IPCOM000046530D
Original Publication Date: 1983-Aug-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 3 page(s) / 42K

Publishing Venue

IBM

Related People

Minshull, JF: AUTHOR [+2]

Abstract

The directly addressable microprocessor storage space of the virtual memory terminal described in [1] is extended by the addition of a random-access memory backing store (RAMBS) to the primary RAM used as the working store or cache of the terminal. All program and user data is accessed from the cache during program execution with page faults at the cache level causing segment transfers between the cache and the RAMBS. The implementation is such that the RAMBS does not need to have the same fast access/cycle time as the primary RAM and accordingly the cost per byte is less. The data management of the RAMBS is the same as for the Cyclic Cache described in [2]. This has the characteristic of providing on-demand space predictably with good response times.

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Extended RAM for Virtual Memory Terminal

The directly addressable microprocessor storage space of the virtual memory terminal described in [1] is extended by the addition of a random-access memory backing store (RAMBS) to the primary RAM used as the working store or cache of the terminal. All program and user data is accessed from the cache during program execution with page faults at the cache level causing segment transfers between the cache and the RAMBS. The implementation is such that the RAMBS does not need to have the same fast access/cycle time as the primary RAM and accordingly the cost per byte is less. The data management of the RAMBS is the same as for the Cyclic Cache described in [2]. This has the characteristic of providing on-demand space predictably with good response times. It also requires minimal data movement to reorganize to a sorted and compacted format because of its double-ended layout. The cache design for use with the RAMBS uses cyclic assignment of space. It compacts fragment space to the allocation and reallocation points depending on the disposition of the fragments with respect to the allocation phase. In contrast to the arrangement in [1], sorting is not employed in the cache which, as it uses first-in, first-out ordering, is never out of sequence. Significant aspects of the operating methods of the RAMBS result from the ability of the microprocessor to execute directly out of backing store RAM. This allows the backing store working status to reside in the backing store at equivalent locations to those occupied by the cache status in the cache. The segment format in the cache and backing store is identical. As a result of these two factors the microcode which is used to run the two stores is largely identical and compact. This has been achieved, even though the operating methods for the two stores are substantially different, by careful definition of the code procedures and store pointers. Store initialization sets the SPFREE value equal to the backing store high address. Segments, paged down from the cache, are allocated space in the backing store from the current SPFREE location in descending address sequence. Segments retain their control chain status when paged between the cache and backing store and only have their control chain status modified while in the cache. Segments are directly or indirectly allocated to a control chain while in the cache through the MAIN; LOCAL; OB...