Dismiss
InnovationQ will be updated on Sunday, Oct. 22, from 10am ET - noon. You may experience brief service interruptions during that time.
Browse Prior Art Database

Extended RAM for Virtual Memory Terminal

IP.com Disclosure Number: IPCOM000046531D
Original Publication Date: 1983-Aug-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 2 page(s) / 15K

Publishing Venue

IBM

Related People

Minshull, JF: AUTHOR [+2]

Abstract

The concept of the virtual memory terminal (VMT) described in [*] is to implement a virtual memory using a random-access store and one or more storage devices, in a hierarchy of access times. The preceding article describes how additional RAM, beyond the 64K RAM of the VMT terminal, can be used to implement a unique level of the storage hierarchy between the primary RAM and a local backing store. Alternatively, additional RAM may be made available by using hardware logic to map 16-bit micro addresses to, for example, 20-bit addresses in a megabyte RAM array. By this means, the primary level of the storage hierarchy consists of 1M bytes directly accessible to the application programs.

This text was extracted from a PDF file.
This is the abbreviated version, containing approximately 44% of the total text.

Page 1 of 2

Extended RAM for Virtual Memory Terminal

The concept of the virtual memory terminal (VMT) described in [*] is to implement a virtual memory using a random-access store and one or more storage devices, in a hierarchy of access times. The preceding article describes how additional RAM, beyond the 64K RAM of the VMT terminal, can be used to implement a unique level of the storage hierarchy between the primary RAM and a local backing store. Alternatively, additional RAM may be made available by using hardware logic to map 16-bit micro addresses to, for example, 20-bit addresses in a megabyte RAM array. By this means, the primary level of the storage hierarchy consists of 1M bytes directly accessible to the application programs. In order to support up to 1M bytes of primary RAM, bits 0-3 of the 16- bit address bus are used (if non-zero) to select one of 15 8-bit mapping registers, and the 8-bit content of the selected mapping register concatenated with bits 4- 15 of the micro address bus produce the 20-bit real address which finally accesses the 1M-byte RAM. The address mapping hardware provides for "register 0" to map implicitly to storage block 0, so that every program using micro addresses '0000' - '0FFF' accesses the same block of primary RAM, in which interrupt handlers and other common system code can be located. In VMT, each compiled application program will have some procedure and some data in fixed storage locations at run time; the exact amount of such fixed procedure and fixed data is determined at compile time, and in general it will be different for each application program. To accommodate this need for fixed storage, the VMT application program loader assigns mapping registers from "register 1" upwards to map statically to the memory address blocks '1000'- '1FFF' upwards, to whatever extent that the application program specifies. The remaining mapping registers are then available for dynamic assignment to 4K blocks containing virtual memory segments. The first mapping register available for dynamic assignment has significance in the description below, and it is referred to as mapping register 'n' hereafter. In order to support a primary RAM of more than 64K bytes, the locator object of VMT is defined to have 3 system states: DISCONNECTED A disconnected locator has bit 0 set to '0' and contains the segment-id of the associated segment. The associated segment may physically be in any level of the storage hierarchy. CONNECTED but UNMAPPED A connected but unmapped locator has bits 0,1 set to '10' and contains the 20-bit address of the associated segment in the primary RAM. Although the segment is physically in the primary RAM, it is not accessible to a program in the micro because there is no known mapping of any 16-bit micro address to the 20-bit primary RAM address. MAPPED A mapped locator has bit 0, 1 set to '11' and contains the 16-bit micro address by which the segment may be accessed, where 4 bits identify a mapping reg...