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High Density Parity-Checking Circuits With Pass Transistors

IP.com Disclosure Number: IPCOM000046555D
Original Publication Date: 1983-Aug-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 2 page(s) / 47K

Publishing Venue

IBM

Related People

Tsai, MY: AUTHOR

Abstract

A parity-checking circuit using pass transistors for error detection is described. This circuit can be implemented as a dynamic circuit in NMOS technology or as a static circuit in CMOS technology. The described parity-checking circuit features advantages of high density and low power. Parity checking is important in a digital computer for error checking. In VLSI design, with conventional XOR gates (Fig. 1) used in parity checking, the circuit tends to occupy large Si area and consume high power. A 32 bit word needs at least 31 XOR circuits for parity checking F = X0+ 0X2+ . . . . . . + . 0X1+ 0 0X31 In order to reduce the power and area of this type of circuit, a new circuit using pass transistors for parity-checking is proposed here.

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High Density Parity-Checking Circuits With Pass Transistors

A parity-checking circuit using pass transistors for error detection is described. This circuit can be implemented as a dynamic circuit in NMOS technology or as a static circuit in CMOS technology.

The described parity-checking circuit features advantages of high density and low power. Parity checking is important in a digital computer for error checking. In VLSI design, with conventional XOR gates (Fig. 1) used in parity checking, the circuit tends to occupy large Si area and consume high power. A 32 bit word needs at least 31 XOR circuits for parity checking F = X0+ 0X2+ . . . . . . + .

0X1+ 0 0X31 In order to reduce the power and area of this type of circuit, a new circuit using pass transistors for parity-checking is proposed here. The implementation can be a dynamic circuit in NMOS (Fig. 2) or a static circuit in CMOS (Fig. 3). The basic idea is that one of the two chains will connect the nodes (Even or Odd) to ground. By the proper circuits, the signal can be sensed. The number of pass transistors which can be cascaded has to be determined by the detailed information of the technology. Four cascaded transistors are used here just for demonstrating the concept. The dynamic NMOS circuits have the advantage of lower power and better performance over the static circuits. However, the precharge does imply circuit overhead. The CMOS circuit is a static circuit. It has the advantage of both low power and...