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Improved Signature Test for VLSI Circuits

IP.com Disclosure Number: IPCOM000046557D
Original Publication Date: 1983-Aug-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 3 page(s) / 27K

Publishing Venue

IBM

Related People

Carter, JL: AUTHOR

Abstract

When testing VLSI (very large-scale integration) circuits using a signature testing technique, a circuit whose responses are incorrect could still have the same signature as a good circuit. The method described herein reduces the chance of this happening. Several methods for testing VLSI chips can be classified as signature methods. Such a method applies a number of test patterns to the inputs of the circuit and accumulates the outputs of the circuit by some data compression device. After all the test patterns have been applied, the signature - the final contents of the accumulator - is examined to see if it agrees with the signature produced by a good chip. Signature testing methods have several advantages over conventional testing in which each output pattern is examined individually.

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Improved Signature Test for VLSI Circuits

When testing VLSI (very large-scale integration) circuits using a signature testing technique, a circuit whose responses are incorrect could still have the same signature as a good circuit. The method described herein reduces the chance of this happening. Several methods for testing VLSI chips can be classified as signature methods. Such a method applies a number of test patterns to the inputs of the circuit and accumulates the outputs of the circuit by some data compression device. After all the test patterns have been applied, the signature - the final contents of the accumulator - is examined to see if it agrees with the signature produced by a good chip. Signature testing methods have several advantages over conventional testing in which each output pattern is examined individually. However, they run the risk that masking may occur. Masking is said to occur if a faulty chip and a good chip behave differently on the test patterns, but the signatures are identical; when masking occurs, the signature testing method will incorrectly conclude that the chip is good, whereas a conventional method would discover that the chip is defective. Several modifications of a Multiple Input Signature Register (MISR), a known signature accumulator 1,Ùare described for which the probability of masking is provably small. An important difference between this and other signature testing methods is that it is not necessary for the chips being tested to satisfy any assumptions about randomness for the technique to be successful. Thus, unlike other methods, the presently described one is immune to so-called "correlated errors." The MISR is depicted in the figure. The input wires to the MISR are probes from a circuit under test (CUT). They could come from the outputs of the CUT or from points internal to the CUT. Another possibility is that the registers of the MISR are actually the internal registers of a LSSD-designed circuit. As each test pattern is run through the CUT, the contents of the k internal 1-bit registers of the MISR are shifted one position, exclusive-ORed with these signals from the circuit being tested, and stored back in the registers. The bit being shifted into the beginning of the string of registers is the exclusive-OR of an output wire and the bits in several carefully chosen registers. These registers are chosen to correspond to the non-zero coefficients of a primitive polynomial of degree k over GF(2)[2]. The MISR must have some control signals (not shown in the diagram) which determine when the wires from the CUT are to be sampled and when the shift operation is to be performed. The registers, exclusive-OR circuits and control circuitry of the MISR can be implemented in any convenient way. The MISR, as described above, is susceptible to masking due to correlated errors. The new feature described here comprises four specific methods of combining the MISR to the circuit being tested. For e...