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Browse Prior Art Database

High Speed Signature Analysis

IP.com Disclosure Number: IPCOM000046562D
Original Publication Date: 1983-Aug-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 2 page(s) / 42K

Publishing Venue

IBM

Related People

Hanson, FA: AUTHOR

Abstract

There is shown and described a new design concept which effectively eliminates the delay caused by two of the gates in an existing signature analysis apparatus. A look-ahead and preprocessing function is provided and, depending on the logic type used in the implementation, a speed enhancement of up to 200 percent is possible. Fig. 1 illustrates typical hardware design used in signature analyzers. Fig. 2 illustrates the enhanced design. The circuit in Fig. 2 can run up to twice the speed of the circuit shown in Fig. 1, due to the two-level look-ahead and data preprocessing functions. The speed of the unit is determined by the propagation delay through the exclusive-OR gates and the 16-bit register. The 16-bit register propagation delay (PDR) is that delay through one cell of the register.

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High Speed Signature Analysis

There is shown and described a new design concept which effectively eliminates the delay caused by two of the gates in an existing signature analysis apparatus. A look-ahead and preprocessing function is provided and, depending on the logic type used in the implementation, a speed enhancement of up to 200 percent is possible. Fig. 1 illustrates typical hardware design used in signature analyzers. Fig. 2 illustrates the enhanced design. The circuit in Fig. 2 can run up to twice the speed of the circuit shown in Fig. 1, due to the two-level look-ahead and data preprocessing functions. The speed of the unit is determined by the propagation delay through the exclusive-OR gates and the 16-bit register. The 16-bit register propagation delay (PDR) is that delay through one cell of the register. If it is further assumed that the propagation delays of the exclusive-OR gate (PDEOR) are identical, then the maximum frequency (FMAX) of the unit in Fig. 1 is the following: Comparing Figs. 1 and 2, it is seen that the latter has three additional flip-flops and the taps on the 16-bit register are moved two bits earlier in time. This gives a two-clock look-ahead feature.

The clock used to clock data in the 16-bit register also is used to clock FF1, FF2 and FF3 . The data on the 16-bit register taps is two clocks early or T-2. The data is preprocessed through the exclusive-OR gates and stored in FF1 and FF2 on the next clock cycle. The outputs of FF1...