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Effective Master-Slave Latch Combination

IP.com Disclosure Number: IPCOM000046568D
Original Publication Date: 1983-Aug-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 2 page(s) / 39K

Publishing Venue

IBM

Related People

St. Clair, JC: AUTHOR

Abstract

For an effective use of dual data port-dual clock master latches M paired with simple slave latches S, being in operation testable in accordance with level sensitive scan design (LSSD) rules, each master latch M is driven by a unique gated clock C. For loading the slave latches S, first all their master latches M are loaded and then all slave latches S are gated together, copying the data in the master latches M into the slave latches S. After that, the master latches M are loaded individually with their appropriate data. So each used latch stores one data bit, and the circuit can be scanned during testing.

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Effective Master-Slave Latch Combination

For an effective use of dual data port-dual clock master latches M paired with simple slave latches S, being in operation testable in accordance with level sensitive scan design (LSSD) rules, each master latch M is driven by a unique gated clock C. For loading the slave latches S, first all their master latches M are loaded and then all slave latches S are gated together, copying the data in the master latches M into the slave latches S. After that, the master latches M are loaded individually with their appropriate data. So each used latch stores one data bit, and the circuit can be scanned during testing. The figure shows master latches M having inputs I, D forming the dual data ports from the data bus and the scanning line, and having two clocking inputs A for the test clock and C for clock C which is gated individually via AND circuits SL1, SL2,...,SLN using select 1, select 2,...,select N signals. The output Q of each master latch M forms a separate output of that latch and the input of its slave latch S, the output Q of each slave latch S forming also a separate output and input to the next master latch M in the chain with the exception of the scanner output of the last slave latch. Via AND circuit SB, clock B is selected by a signal (select S) for gating all slave latches S together, using the only clocking input B of the simple slave latches S. This slave-gating clock is guided to a primary output for testing purpo...