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Frequency Divider and Phase Shifter for Generating Symmetrical Waveforms

IP.com Disclosure Number: IPCOM000046572D
Original Publication Date: 1983-Aug-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 2 page(s) / 41K

Publishing Venue

IBM

Related People

Hernandez, I: AUTHOR

Abstract

To divide by an integer n, this frequency divider consists of n flip-flops: FF1, FF2,...,FFn. As shown in Fig. 1, the incoming frequency f is fed to one input of an exclusive-OR gate 10 and to a delay circuit 11. The output fd of delay circuit 11 forms the second input of exclusive-OR gate 10. On output 12, a pulse train fp with twice the frequency of f is generated and fed as clocking pulses to the CLK inputs of the flip-flops FF1 to FFn. Their outputs Q1, Q2,...,Qn are fed to the data inputs D2, D3,...,Dn, and D1, with the exception that the signal Qn of the last flip-flop FFn is gated via an inverter 13 to the data input D1 of flip-flop FF1. Signal Q1 of FF1 provides the desired frequency and is in phase with original frequency f, whereas signals Q2,...

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Frequency Divider and Phase Shifter for Generating Symmetrical Waveforms

To divide by an integer n, this frequency divider consists of n flip-flops: FF1, FF2,...,FFn. As shown in Fig. 1, the incoming frequency f is fed to one input of an exclusive-OR gate 10 and to a delay circuit 11. The output fd of delay circuit 11 forms the second input of exclusive-OR gate 10. On output 12, a pulse train fp with twice the frequency of f is generated and fed as clocking pulses to the CLK inputs of the flip-flops FF1 to FFn. Their outputs Q1, Q2,...,Qn are fed to the data inputs D2, D3,...,Dn, and D1, with the exception that the signal Qn of the last flip-flop FFn is gated via an inverter 13 to the data input D1 of flip-flop FF1. Signal Q1 of FF1 provides the desired frequency and is in phase with original frequency f, whereas signals Q2,...,Qn are phase-shifted by 360OE/2n when f is symmetrical but also have a frequency f/n. The system reset signal is tied to the CLR input of each of the flip-flops FF1, FF2,...,FFn so that upon beginning the divide operation, a reset can be performed to assure that the output Q1 of flip- flop FF1 is in synchronism with the incoming frequency f. Fig. 2 shows the waveforms for the case n=3, i.e., division by 3. The delay time td between the incoming frequency f and the delayed frequency fd should, in accordance with the requirements of the flip-flops, be chosen such that the pulse train fp is long enough to clock the flip-flop. The three bottom...