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Sequential Access Indication for Microprocessors

IP.com Disclosure Number: IPCOM000046574D
Original Publication Date: 1983-Aug-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 1 page(s) / 12K

Publishing Venue

IBM

Related People

Wright, CG: AUTHOR

Abstract

A signal indicating a sequential memory access is generated by a processor or other device which accesses storage. This enables improved performance in memory accessing time and simplifies the detection of a sequential access in comparison to having the storage controller make this detection. In computer systems, attempts to enhance performance often center on taking advantage of the facts that Instruction Fetches utilize a large portion of storage bandwidth, and these accesses are largely sequential in nature. That is, if there is an access to address N, there is a much greater than random probability that the next access will be at address N+1. One performance improvement technique has been to do wide memory accesses (wider than the processor requires) and save the unused information.

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Sequential Access Indication for Microprocessors

A signal indicating a sequential memory access is generated by a processor or other device which accesses storage. This enables improved performance in memory accessing time and simplifies the detection of a sequential access in comparison to having the storage controller make this detection. In computer systems, attempts to enhance performance often center on taking advantage of the facts that Instruction Fetches utilize a large portion of storage bandwidth, and these accesses are largely sequential in nature. That is, if there is an access to address N, there is a much greater than random probability that the next access will be at address N+1. One performance improvement technique has been to do wide memory accesses (wider than the processor requires) and save the unused information. Subsequent accesses cause an address comparison, and if the desired data is already available, it is read out and no storage access is done. Another technique is to utilize the "page-mode" capability of many semiconductor random-access memories. In this mode, once a location is accessed, other locations in the same "page" are available in less time. To take advantage of this, the storage control logic must do address comparisons to recognize sequential accesses. The present technique of having the processor generate the sequential access signal allows this information to be furnished when the address goes out from the processor or o...