Browse Prior Art Database

Time Sharing of Logic Functions in LSSD Design

IP.com Disclosure Number: IPCOM000046599D
Original Publication Date: 1983-Aug-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 2 page(s) / 40K

Publishing Venue

IBM

Related People

Hanna, SD: AUTHOR

Abstract

The LSSD (Level Sensitive Scan Design) rule requires that a latch may not feed the data port of another latch if the same clock signal sets both latches. This article describes a technique for avoiding the cost of additional components to meet this design rule in a time shared circuit by calling real system clocks "clock enables," and adding LSSD clock pins to meet LSSD checker program requirements. Real system clocks (PA, PB) are 'ANDed' with LSSD clocks (PA1I, PA2I, PBlI, PB2I) to generate the actual clocks to the latches, as shown in Fig. 1. LSSD clocks are held high during system operation, and real system clocks are used as clock enables during LSSD test. Fig.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 100% of the total text.

Page 1 of 2

Time Sharing of Logic Functions in LSSD Design

The LSSD (Level Sensitive Scan Design) rule requires that a latch may not feed the data port of another latch if the same clock signal sets both latches. This article describes a technique for avoiding the cost of additional components to meet this design rule in a time shared circuit by calling real system clocks "clock enables," and adding LSSD clock pins to meet LSSD checker program requirements. Real system clocks (PA, PB) are 'ANDed' with LSSD clocks (PA1I, PA2I, PBlI, PB2I) to generate the actual clocks to the latches, as shown in Fig. 1. LSSD clocks are held high during system operation, and real system clocks are used as clock enables during LSSD test. Fig. 2 shows an adder circuit which apparently violates the above-named LSSD rule in that the clock signals PA and PB are on latches that feed the adder as well as on adder output latches. However, since the adder is time shared, that is, the inputs to the adder are switched with the system signal XA, the system does not violate the spirit of the rules since the output of latch X does not feed latch Y during the time period when the PA clock occurs. For example, logic circuit 10 is enabled when XA=1, but latch Y is clocked when XA=0. Logic circuit 11 is enabled when XA=1, but latch Z is clocked when XA=0.

1

Page 2 of 2

2

[This page contains 6 pictures or other non-text objects]