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Narrow Base-Width Lateral PNP Fabrication

IP.com Disclosure Number: IPCOM000046616D
Original Publication Date: 1983-Aug-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 2 page(s) / 70K

Publishing Venue

IBM

Related People

Bhatia, HS: AUTHOR [+4]

Abstract

A lateral PNP device fabrication method is described. The resultant device has an extremely narrow base width for the lateral PNP device compared to currently known lateral PNP base widths and is between about 5 to 8 micrometers. Fig. 1 shows the starting structure with the P substrate 10, an Nsubcollector region 12, an N-epitaxial layer 14, recessed oxide isolation (ROI), and a silicon dioxide surface layer 16. A chemical vapor deposited (CVD) layer 18 of between about 150-160 nanometers of Si3N4 is formed over layer 16. An appropriate resist mask 20 with openings therein for planned P areas is formed by standard lithographic and etching techniques and is shown in Fig. 2. The mask is used to reactive ion etch (RIE) layers 18 and 16. Etching is continued into the monocrystalline silicon to form wells 22.

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Narrow Base-Width Lateral PNP Fabrication

A lateral PNP device fabrication method is described. The resultant device has an extremely narrow base width for the lateral PNP device compared to currently known lateral PNP base widths and is between about 5 to 8 micrometers. Fig. 1 shows the starting structure with the P substrate 10, an Nsubcollector region 12, an N-epitaxial layer 14, recessed oxide isolation (ROI), and a silicon dioxide surface layer 16. A chemical vapor deposited (CVD) layer 18 of between about 150-160 nanometers of Si3N4 is formed over layer 16. An appropriate resist mask 20 with openings therein for planned P areas is formed by standard lithographic and etching techniques and is shown in Fig. 2. The mask is used to reactive ion etch (RIE) layers 18 and 16. Etching is continued into the monocrystalline silicon to form wells 22. The resist is removed. At this point of the process there are two alternate methods to form the desired lateral PNP. One is illustrated in Figs. 3-6 and the other in Figs. 7-9. In the first alternative, a 30-nanometer SiO2 layer 24 is formed followed by a 100-nanometer Si3N4 layer
26. Anisotropic etching of these layers removes the horizontal layers and leaves the vertical sidewalls, as seen in Fig. 3. A 200-nanometer SiO2 layer 28 is thermally grown on exposed silicon, as seen in Fig. 4. Next, there is wet etching of sidewalls 24, 26 and surface layers 16, 18, leaving only silicon dioxide layer 28 remaining at the bottom...