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Metal Lift-Off Process for Submicron Spacings

IP.com Disclosure Number: IPCOM000046617D
Original Publication Date: 1983-Aug-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 2 page(s) / 51K

Publishing Venue

IBM

Related People

Malaviya, SD: AUTHOR

Abstract

The method for forming integrated circuits with this structure involves providing a silicon body and then forming a first insulating layer which may be a composite layer of silicon dioxide 10 and silicon nitride 11 on a major surface of the silicon body 12. A layer of polycrystalline silicon is formed thereover. Openings are made in the polycrystalline silicon layer by reactive ion etching which results in the structure having substantially horizontal surfaces and substantially vertical surfaces. A second insulating layer is then formed on both the substantially horizontal surfaces and substantially vertical surfaces.

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Metal Lift-Off Process for Submicron Spacings

The method for forming integrated circuits with this structure involves providing a silicon body and then forming a first insulating layer which may be a composite layer of silicon dioxide 10 and silicon nitride 11 on a major surface of the silicon body 12. A layer of polycrystalline silicon is formed thereover. Openings are made in the polycrystalline silicon layer by reactive ion etching which results in the structure having substantially horizontal surfaces and substantially vertical surfaces. A second insulating layer is then formed on both the substantially horizontal surfaces and substantially vertical surfaces. Reactive ion etching of this second insulating layer substantially removes the horizontal layers and provides a narrow dimensioned dielectric pattern of regions or studs upon the major surface of the silicon body. The remaining polycrystalline silicon layer is then removed by etching to leave the free-standing narrow dimensioned regions or studs 15 on the major surfaces of the silicon body between device contacts and in other places outside the device, as seen in Fig. 1. The stud height is made greater than the thickness of the first metal to be deposited. Optionally, during the formation of the stud, the upper silicon nitride layer 11 may be replaced with silicon oxynitride to permit the formation of a small bird's beak 16 over the top of the stud 15, as seen in Fig. 1. PtSi is formed over device contacts (not shown) as usual, followed by evaporation of first level metal 18, including ba...