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Microwatt CCG Logic Circuit With JFET Feedback Loop

IP.com Disclosure Number: IPCOM000046630D
Original Publication Date: 1983-Aug-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 2 page(s) / 30K

Publishing Venue

IBM

Related People

Balyoz, J: AUTHOR [+2]

Abstract

Fig. 1 shows a CCG (Current-Controlled Gate) logic circuit with an added JFET feedback loop. The operation of the CCG circuit alone is described in detail in [*]. When the CCG logic circuit is designed to operate in a low microwatt power region (100-150 microwatts), a very high value resistor, connected to the base of transistor T5, is required. The implementation of such high valued semiconductor resistors (150-200 kilohm) on VLSI chips is impractical. The use of the JFET feedback loop, formed by the device T6 in Fig. 1, provides a solution to this problem. An additional improvement to the CCG circuit described in [*] is made in the circuit shown in Fig. 1. Note that the emitter and collector of device T3, which provide dynamic capacitive coupling, are shorted together instead of shorting the emitter and base.

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Microwatt CCG Logic Circuit With JFET Feedback Loop

Fig. 1 shows a CCG (Current-Controlled Gate) logic circuit with an added JFET feedback loop. The operation of the CCG circuit alone is described in detail in
[*]. When the CCG logic circuit is designed to operate in a low microwatt power region (100-150 microwatts), a very high value resistor, connected to the base of transistor T5, is required. The implementation of such high valued semiconductor resistors (150-200 kilohm) on VLSI chips is impractical. The use of the JFET feedback loop, formed by the device T6 in Fig. 1, provides a solution to this problem. An additional improvement to the CCG circuit described in [*] is made in the circuit shown in Fig. 1. Note that the emitter and collector of device T3, which provide dynamic capacitive coupling, are shorted together instead of shorting the emitter and base. This technique provides larger coupling capacitance which, in turn, results in improved performance of the circuit. The circuit shown in Fig. 1 was analyzed using ASTAP, with a three-stage logic gate chain, the second stage of which is the test stage. The results obtained from the analysis for various width-to-length ratios (W/L) of the JFET are listed in the table below. The voltage waveforms of this sample design are shown in Fig. 2. The waveforms show acceptable voltage levels and good operation of this CCG circuit with the JFET feedback loop.

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In comparing the results given in the table...