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Browse Prior Art Database

Latent Scheduling Macromodular Machine

IP.com Disclosure Number: IPCOM000046639D
Original Publication Date: 1983-Aug-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 4 page(s) / 38K

Publishing Venue

IBM

Related People

Coleman, JJ: AUTHOR [+2]

Abstract

This is a system for analyzing large circuit networks. More particularly, this is an apparatus and method for verifying the adequacy of designs of circuits having a very large number of very small, closely spaced elements such as are found on large-scale integration (LSI) chips. As part of the design phase of LSI chips, manufacturers commonly study various designs by simulating them in order to help confirm their practicality and manufacturability. The simulations, which may utilize special purpose hardware or programmed general purpose computers, can help to identify logical problems (such as, for example, race conditions) and environmental problems (such as, for example, excess power dissipation) which could lead to malfunction and/or failure of the LSI chip.

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Latent Scheduling Macromodular Machine

This is a system for analyzing large circuit networks. More particularly, this is an apparatus and method for verifying the adequacy of designs of circuits having a very large number of very small, closely spaced elements such as are found on large-scale integration (LSI) chips. As part of the design phase of LSI chips, manufacturers commonly study various designs by simulating them in order to help confirm their practicality and manufacturability. The simulations, which may utilize special purpose hardware or programmed general purpose computers, can help to identify logical problems (such as, for example, race conditions) and environmental problems (such as, for example, excess power dissipation) which could lead to malfunction and/or failure of the LSI chip. The typical simulation system takes into account every interconnection of every element in the LSI network and generates data concerning the network and its constituent elements over a long period of time. Current techniques, whether embodied in special-purpose hardware or programmed general-purpose hardware, require vast storage resources to hold all of the element interconnection data and, because of the number and complexity of the necessary computations, require a long time to provide a reasonably complete simulation analysis of an LSI circuit design. Since an LSI circuit design may go through many iterations between the first design and the one that is finally accepted for manufacturing, and because each of the iterations will typically be subjected to the simulation analysis, the very large storage and time requirements of prior-art analysis apparatus and methods results in the simulation being a significant part of the total expense in designing and manufacturing LSI chips. The circuit analysis machine described herein exploits the modular nature of VLSI circuits and consists of modular hardware designed to enable a VLSI circuit entity to be modeled quickly and then analyzed in realtime. The hardware is assembled such that each circuit model is a pluggable processor or hardware entity, i.e., a circuit model for a transistor is a printed circuit card or a circuit model for a latch is a card, etc. These processors are wired in parallel through a hierarchical cross-point scheme (programmable) and each contains a hierarchy of the VLSI design being modeled and analyzed. The hardware is patterned after analysis programs that also exploit circuit modularity, viz., the MACRO circuit analysis program. However, these programs did not handle the complex (circuit size) problems proposed for solution by the herein-described technique. Each card or module is "called" through the cross-point switch, tested for latency and, if "active", the model is executed and provides signals back to the switch and, if "inactive", returns previously found signals. The signals are voltage and current variables derived through the execution of the equation sol...