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FIFO Buffer Memory Comprising a Random-Access Memory and Two Pointers

IP.com Disclosure Number: IPCOM000046644D
Original Publication Date: 1983-Aug-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 2 page(s) / 76K

Publishing Venue

IBM

Related People

D'Hervilly, G: AUTHOR [+2]

Abstract

The FIFO (first-in, first-out) buffer function is more and more required in various digital systems, particularly to interface a synchronous subsystem. The firmware (or software) approach requires program or microprogram execution and thence delay. On the other hand, a battery of shift registers might be implemented to achieve this function, but it is known to be silicon and power consuming. Therefore, herein is proposed a hardwired implementation of a FIFO, which saves both silicon area and power dissipation, on the one hand, and reduces time delay, on the other hand. The FIFO function comprises two pointers and a RAM (random-access memory), which has a latched output (L. RAM). The circuit is shown in Fig. 1.

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FIFO Buffer Memory Comprising a Random-Access Memory and Two Pointers

The FIFO (first-in, first-out) buffer function is more and more required in various digital systems, particularly to interface a synchronous subsystem. The firmware (or software) approach requires program or microprogram execution and thence delay. On the other hand, a battery of shift registers might be implemented to achieve this function, but it is known to be silicon and power consuming. Therefore, herein is proposed a hardwired implementation of a FIFO, which saves both silicon area and power dissipation, on the one hand, and reduces time delay, on the other hand. The FIFO function comprises two pointers and a RAM (random-access memory), which has a latched output (L. RAM). The circuit is shown in Fig. 1. It is to be noted that the asterisked items are interface primary I/O's of the whole device; the other terminals represent internal connections only. The circuit is basically comprised of a "latched output" RAM (which indicates that the memory includes an output register) and two pointers RP (read pointers) and WP (write pointers), operating as the Read Address Working Register and the Write Address Working Register, respectively. Each pointer consists of a master-slave register feeding into and fed back by a 1-incrementing random logic IN. The whole design follows the so-called Level Sensitive Scan Design (LSSD) (as described, for example, in Electronics) March 15, 1979, pages 108-110, which requires conditions in the structure of the logic and the registers for working with each other. The special output LSO (LSSD Shift Out) and the special inputs Ack, Bck and Cck (where ck represents clock) and LSI (LSSD Shift In) fulfill the LSSD conditions. Due to the structure of the LSSD rule...