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Set of SHIFT Registers Formed From a FIFO Buffer Memory

IP.com Disclosure Number: IPCOM000046645D
Original Publication Date: 1983-Aug-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 3 page(s) / 48K

Publishing Venue

IBM

Related People

D'Hervilly, G: AUTHOR [+2]

Abstract

In digital signal processing it is often desired to have a battery of shift registers working as a buffer or a delay line. Normally this problem may be solved by implementing a series of master slave latches sequentially connected; however, this solution is recognized as requiring much silicon area and dissipates much power. When minimizing both power dissipation and silicon area is a must, the following implementation based on a FIFO (first-in, first-out) buffer memory, such as described in the preceding article, which not only considerably reduces power dissipation and silicon area but also adds flexibility in case of implementing a specially timed buffer. The basic principle of a shift register set is shown in Fig. 1, and the timing is shown in Fig. 2. Information encoded on "N" bits arrives on the IN.BUS at each cycle.

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Set of SHIFT Registers Formed From a FIFO Buffer Memory

In digital signal processing it is often desired to have a battery of shift registers working as a buffer or a delay line.

Normally this problem may be solved by implementing a series of master slave latches sequentially connected; however, this solution is recognized as requiring much silicon area and dissipates much power. When minimizing both power dissipation and silicon area is a must, the following implementation based on a FIFO (first-in, first-out) buffer memory, such as described in the preceding article, which not only considerably reduces power dissipation and silicon area but also adds flexibility in case of implementing a specially timed buffer. The basic principle of a shift register set is shown in Fig. 1, and the timing is shown in Fig. 2. Information encoded on "N" bits arrives on the IN.BUS at each cycle. Let us suppose that IN.BUS represents "level 0" and OUT.BUS represents the output of "level L"; then, if information "DO" is present on IN.BUS at time "TO", one cycle later it will be clocked into both the master (M) and slave (S) latches of level 1; two cycles later, it is present in level 2, etc., and L cycles later, it is in level L and therefore appears on OUT.BUS. Data on IN.BUS must be stable during C.CK = "ON" and may change during C.CK = "OFF". The output of each M latch of each bit is changing during C.CK = ON and stable during C.CK = OFF. Output of each S-latch (slave) of each bit is changing during B.CK = ON and stable during B.CK = OFF. The input of each latch must be stable during its own clock = ON and may change during its own clock = OFF.

Therefore, the interleaving of C. and B. Clocks, as shown in Fig. 2, insures proper working conditions: - At each odd subcycle, all slave-information is simultaneously clocked into the M-latches of the next levels - At each even subcycle, all master-information is simultaneously cl...