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Reducing Time Losses in the Forced High-Impedance State of Tristate Drivers Operating in the SYSTEM Mode

IP.com Disclosure Number: IPCOM000046652D
Original Publication Date: 1983-Aug-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 2 page(s) / 54K

Publishing Venue

IBM

Related People

Blum, A: AUTHOR

Abstract

When tristate drivers connected to a common output line are tested, only one driver may be active, while the others are forced to the high-impedance state. Therefore, each driver has a first input FA, through which it is activated, and a second input HIS, through which it is forced to the high-impedance state. Input HIS is fed by a circuit which is designed as a shift register stage to ensure that the monolithically integrated circuits may be tested without any difficulty. For forming a shift register, this shift register stage is connected to other shift register stages consisting of master-slave latches. As the tristate driver is forced to the high-impedance state not only during testing but also in the normal system mode, the signal is noticeably delayed when passing the shift register stage preceding input HIS.

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Reducing Time Losses in the Forced High-Impedance State of Tristate Drivers Operating in the SYSTEM Mode

When tristate drivers connected to a common output line are tested, only one driver may be active, while the others are forced to the high-impedance state. Therefore, each driver has a first input FA, through which it is activated, and a second input HIS, through which it is forced to the high-impedance state. Input HIS is fed by a circuit which is designed as a shift register stage to ensure that the monolithically integrated circuits may be tested without any difficulty. For forming a shift register, this shift register stage is connected to other shift register stages consisting of master-slave latches. As the tristate driver is forced to the high-impedance state not only during testing but also in the normal system mode, the signal is noticeably delayed when passing the shift register stage preceding input HIS. This applies also if during the system mode the information, rather than being clock-shifted as during testing, passes this stage in response to a suitable plus potential continuously applied to the clock line. To avoid such signal delays, the tristate driver circuit of Fig. 1 is supplemented by a master-slave latch shift register stage shown in the lower portion of this figure. For switching the tristate driver to the high-impedance state during testing, a low potential is applied to the input TEST DATA IN of the master latch, whereas for switching...