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Browse Prior Art Database

Program Status Latch

IP.com Disclosure Number: IPCOM000046672D
Original Publication Date: 1983-Aug-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 3 page(s) / 70K

Publishing Venue

IBM

Related People

Crosthwait, WR: AUTHOR [+4]

Abstract

In a time-domain multiplex communications controller, a significant amount of the control operation is performed with software. Since the synchronization of a local station's transmissions over the TDMA (Time Domain Multiple Access) link must be precisely maintained with respect to the timing of other stations communicating on the link, it is important to detect control software failures in the local station as early as is possible in order to avoid making transmissions over the TDMA link during periods when synchronization is being lost. The program status latch invention described herein enables the periodic monitoring of the "health" of the control software within a station and the rapid shutdown of transmissions over the TDMA link when software failures are detected. The figure shows the program status latch invention.

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Program Status Latch

In a time-domain multiplex communications controller, a significant amount of the control operation is performed with software. Since the synchronization of a local station's transmissions over the TDMA (Time Domain Multiple Access) link must be precisely maintained with respect to the timing of other stations communicating on the link, it is important to detect control software failures in the local station as early as is possible in order to avoid making transmissions over the TDMA link during periods when synchronization is being lost. The program status latch invention described herein enables the periodic monitoring of the "health" of the control software within a station and the rapid shutdown of transmissions over the TDMA link when software failures are detected. The figure shows the program status latch invention. The control processor 2 executes the control software which maintains the timing and acquisition operations as well as other functions which are performed by the TDMA station. The control processor outputs an indication on line 3 that a particular monitoring point, in the control software being executed therein, has just been passed. If the control software in the control processor 2 is operating as intended, the signal on line 3 will be periodic in nature. This signal is referred to as the monitoring signal and is passed through the timing and acquisition logic 4 to the timing and acquisition command decoder 6 and is output on line 8 as the load PSL pulse. The load PSL pulse on line 8 is input through the control logic 29 to the reset line 36 of the cascaded flip-flops 30, 32, and 34 in the staging logic 25. The load PSL pulse 8 is also applied as an input to the four-bit program status latch counter 24. Each time the monitoring point is passed in the control software being executed in the control processor 2, the monitoring signal is output on line 3 and causes a load PSL pulse to be output on line 8 to be applied as the reset pulse to the flip- flops 30, 32 and 34 and to be applied as the load pulse to the counter 24. This causes the counter 24 to load the programmable preset value from the register
26. A transmit superframe synchronization signal is received by all of the TDMA stations communicating over the link, and this synchronization signal is periodic and serves as a network-wide timing source. A transmit superframe synchronization signal is input on line 14 to both the short counter 18 and the long counter 20. During normal operation, the clock enable select logic 22 is set to pass the output from the short counter 18 as the input to the counter 24 which is to...