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Ternary Logic Memory Elements

IP.com Disclosure Number: IPCOM000046681D
Original Publication Date: 1983-Aug-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 2 page(s) / 66K

Publishing Venue

IBM

Related People

Maholick, AW: AUTHOR

Abstract

The ternary equivalents of several, commonly used memory elements are described. Figs. 1A and 1B illustrate a master-slave, set-reset flip-flop. The state of the master flip-flop is changed at clock time T and is transferred to the slave at the not-clock T time, i.e., on the inverted clock time delayed one pulse, T+1. Fig. 1B shows a variation where the not-clock time is eliminated and replaced with internally derived clocking. The logic is self-explanatory, and the function of the ternary inverter 1 is described in the mnemonic table 2 in Fig. 1B. A ternary delay element, such as a delay flip-flop (called a "D" flip-flop or shift cell), is the simplest of memory elements to describe. The output is simply that of the input, delayed one clock time. A circuit diagram is shown in Fig. 2.

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Ternary Logic Memory Elements

The ternary equivalents of several, commonly used memory elements are described. Figs. 1A and 1B illustrate a master-slave, set-reset flip-flop. The state of the master flip-flop is changed at clock time T and is transferred to the slave at the not-clock T time, i.e., on the inverted clock time delayed one pulse, T+1. Fig. 1B shows a variation where the not-clock time is eliminated and replaced with internally derived clocking. The logic is self-explanatory, and the function of the ternary inverter 1 is described in the mnemonic table 2 in Fig. 1B. A ternary delay element, such as a delay flip-flop (called a "D" flip-flop or shift cell), is the simplest of memory elements to describe. The output is simply that of the input, delayed one clock time. A circuit diagram is shown in Fig. 2. A master-slave flip-flop 3 identical to that contained in either Fig. 1A or 1B, where the overall master and slave circuits are taken together as block 3, is utilized. Again, the logic is self-explanatory. A ternary cycler analogous to a binary trigger is shown in Fig. 3. The various input gates 5 and the invert function 1 are combined with another master-slave flip-flop circuit 3. The values for the input and output are described by the Table 4 which is part of Fig. 3. When the input C is at a one level, at a clock time T, the output will cycle one state forward. When the input is at the two level voltage at clock time T, the output will cycle two stat...