Browse Prior Art Database

Asynchronous Clock Switching Filter

IP.com Disclosure Number: IPCOM000046710D
Original Publication Date: 1983-Aug-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 2 page(s) / 84K

Publishing Venue

IBM

Related People

Bakken, KL: AUTHOR [+3]

Abstract

In many direct-access storage devices (DASD) the interface between device and attachment provides a serial data port and corresponding read and write file clocks. In a level sensitive scan design (LSSD) two non-overlapping clocks must be generated from the file read clock or the file write clock. Depending on the operation required from the DASD device, the file clock used must switch from one to the other within a specified number of cycles (usually 2-3 cycles). A typical clock switching circuit is shown in Fig. 1. The "gate read/write clock" signals, which are externally generated, are used to select between the DASD read and write clocks for clocking the internal LSSD latches. Blocks 4 through 11 are used to produce non-overlapping LSSD clock pulses.

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Asynchronous Clock Switching Filter

In many direct-access storage devices (DASD) the interface between device and attachment provides a serial data port and corresponding read and write file clocks. In a level sensitive scan design (LSSD) two non-overlapping clocks must be generated from the file read clock or the file write clock. Depending on the operation required from the DASD device, the file clock used must switch from one to the other within a specified number of cycles (usually 2-3 cycles). A typical clock switching circuit is shown in Fig. 1. The "gate read/write clock" signals, which are externally generated, are used to select between the DASD read and write clocks for clocking the internal LSSD latches. Blocks 4 through 11 are used to produce non-overlapping LSSD clock pulses. Since the read and write clocks supplied by the DASD device are asynchronous, a clock spike can occur on either of the two generated LSSD clocks when the switch occurs. When a clock pulse occurs which is less than the minimum clock pulse width for which the LSSD latches were designed, the latches may oscillate, resulting in an unknown state. A worst-case timing example of this is shown in Fig. 2. The invalid clock pulses in this example are caused by the switch between the read and write clocks. Since the write clock was active at the time of the switch, the +L2 clock immediately went inactive, causing an invalid clock pulse. Then when the write clock went inactive immediately following the switch, an invalid +L1 clock pulse also occurred. These invalid clocks are filtered out by the asynchronous clock switching filter circuit to prevent the LSSD latches from going into oscillation. The asynchronous clock switching filter circuit consists of two latches. The first latch allows the clock switch to occur only during the inactive portion of the clock presently selected. This prevents an invalid +L2 clock pulse. The second latch detects the transition when switching from one asynchronous clock...