Browse Prior Art Database

Sidewall Oxide Structure and Method for Polysilicon Gate Devices to Minimize Consumption of Field Oxide

IP.com Disclosure Number: IPCOM000046738D
Original Publication Date: 1983-Aug-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 2 page(s) / 25K

Publishing Venue

IBM

Related People

Blum, JM: AUTHOR [+5]

Abstract

This publication describes a structure that minimizes the amount of field oxide that is consumed during the formation of spacer oxides on the vertical sidewalls of a polysilicon gate device. The procedure for fabricating this structure is as follows: Step 1. Carry out a conventional polysilicon gate process up to the polysilicon etching step. Use an anisotropic etching process, for example, RIE (reactive ion etch), to produce vertically etched walls. Step 2. Strip the resist etch mask. Step 3. Ion implant an n-type impurity for the lightly doped source and drain. Step 4. Deposit a thin film that has the following properties: a) the film is an insulator.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 72% of the total text.

Page 1 of 2

Sidewall Oxide Structure and Method for Polysilicon Gate Devices to Minimize Consumption of Field Oxide

This publication describes a structure that minimizes the amount of field oxide that is consumed during the formation of spacer oxides on the vertical sidewalls of a polysilicon gate device. The procedure for fabricating this structure is as follows: Step 1.

Carry out a conventional polysilicon gate process up to the polysilicon etching step. Use an

anisotropic etching process, for example, RIE (reactive

ion etch), to produce vertically etched walls. Step 2. Strip the resist etch mask. Step 3. Ion implant an n-type impurity for the lightly doped source and drain. Step 4. Deposit a thin film that has the following properties:

a) the film is an insulator.

b) the etch rate of the film is much lower

than the etch

rate of CVD (chemical Vapor deposited) SiO2

using an anisotropic etching process.

c) the material can be etched with another

anisotropic etching process. Step 5. Deposit CVD SiO2 with the thickness determined by the sidewall oxide thickness that is required. Step 6. Etch anisotropically the CVD SiO2 using the etching process that is selective against the thin

underlying film. The underlying film serves as an etch

stop for the CVD oxide and so prevents consumption of

field oxide during the overetching of the CVD oxide

that is required to accommodate nonuniformity in the

CVD oxide and in the etching process. Step 7. Etch anisotropically the film that served...