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Three-Point-Powered Three-Junction Current Injection Device

IP.com Disclosure Number: IPCOM000046745D
Original Publication Date: 1983-Aug-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 3 page(s) / 80K

Publishing Venue

IBM

Related People

Kadlec, J: AUTHOR

Abstract

Feeding the currents from the power supply not only into the injection points, but also into the center point between the inductances, brings substantial performance benefits to Josephson junction logic. Three junction current injection devices (CIDs) have some features which make them only marginally operable in the statistical worst case. This limitation results from the following points: 1) for a given m (Fig. 1), the shape of the threshold curve (i.e., operating window and squareness) is optimum for a certain value of a=L $ I0/D0 (m=3, a=0.38; m=4, a=0.30; m=5, a=0.26).

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Three-Point-Powered Three-Junction Current Injection Device

Feeding the currents from the power supply not only into the injection points, but also into the center point between the inductances, brings substantial performance benefits to Josephson junction logic. Three junction current injection devices (CIDs) have some features which make them only marginally operable in the statistical worst case. This limitation results from the following points: 1) for a given m (Fig. 1), the shape of the threshold curve (i.e., operating window and squareness) is

optimum for a certain value of a=L $ I0/D0 (m=3,

a=0.38; m=4, a=0.30; m=5, a=0.26). 2) being in this optimum, the shape of the threshold curve improves with increasing m; 3) the sensitivity of the threshold curve to deviations of parameters from their nominal values

decreases with increasing m; 4) the size of the device decreases with increasing m. Consequently, one should strive for a design at

large m and optimized value of a. However, 5) the "soft" (1,1)mode gets out of control for large m and/or large a; this mode, which was not recognized

before, may prevent reliable switching of the device

into the voltage state in the full-selected regime. As a result of these conflicting requirements, the designer has to accept a compromise (m=3, a=0.35) in order to be able to control the (1,-1)-mode in the high-current, high-inductance SEC (statistical extreme case) on the high-current chip. However, designing for a low m and away from the optimum a, the shape of the threshold curve (and still more of the noise curve) in the low-current, low-inductance SEC on the low-current chip is strongly deteriorated, which results in the marginal performan...