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Beta-Compensated Current Mirror Circuit

IP.com Disclosure Number: IPCOM000046763D
Original Publication Date: 1983-Aug-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 2 page(s) / 30K

Publishing Venue

IBM

Related People

Myron, DD: AUTHOR [+2]

Abstract

The present circuit is for compensating significant changes in transistor Beta (linear current gain) which can cause inaccuracies in current mirror circuits. Current mirroring is a circuit technique often used in the design of current sources and voltage-to-current converters in integrated circuits. The present circuit compensates for varying base currents (Ib) in current mirror legs. This base current is a main contributor of error in current mirror circuits and increases with low transistor Beta (b). The technique involves converting an input current IIN into Vbe voltage and then using this bias voltage to produce a similar current I2 on adjacent transistors of the same geometry. A typical circuit is shown in Fig. 1.

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Beta-Compensated Current Mirror Circuit

The present circuit is for compensating significant changes in transistor Beta (linear current gain) which can cause inaccuracies in current mirror circuits. Current mirroring is a circuit technique often used in the design of current sources and voltage-to-current converters in integrated circuits. The present circuit compensates for varying base currents (Ib) in current mirror legs. This base current is a main contributor of error in current mirror circuits and increases with low transistor Beta (b). The technique involves converting an input current IIN into Vbe voltage and then using this bias voltage to produce a similar current I2 on adjacent transistors of the same geometry. A typical circuit is shown in Fig.
1. The collector current I2 is dependent on the value of the transistor b and on the number n of current sources in the circuit. The relationship is as follows:

(Image Omitted)

In applications where accurate tracking between IIN and I2 is required, the b and n dependency shown above can cause large errors. In current semiconductor technologies, NPN transistor b can be as low as 30. In such cases, the current error in I2 could be 27% (Fig. 1). The new circuit, shown in Fig. 2, is designed to remove the absolute b dependency between IIN and I2 (Fig. 1). Although the second-order effects contributed by the relative b tracking between two transistors on the same circuit chip are still present, the error can be minim...