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Phase-Locked Loop Provides Rapid Acquisition of a Noisy Signal

IP.com Disclosure Number: IPCOM000046766D
Original Publication Date: 1983-Aug-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 3 page(s) / 36K

Publishing Venue

IBM

Related People

Edgar, AD: AUTHOR

Abstract

This technique offers a superior way of acquiring phase lock of a phase-locked loop onto a noisy signal from an initially unlocked state. The method uses a quadrature detector, freezing the phase feedback quadrature signal component when the other quadrature signal component is negative. The portion of Fig. 1 above the dotted line illustrates a conventional phase-locked loop (PLL). The present technique adds the elements below the dotted line which are a second multiplier operating with the reference signal delayed 90Œ, and a zero-order hold which freezes the output of the first multiplier when the output of the second multiplier is negative. The second multiplier yields the other of the two outputs of what is called a "quadrature demodulator". The two outputs provide effective "real" and "imaginary" signals.

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Phase-Locked Loop Provides Rapid Acquisition of a Noisy Signal

This technique offers a superior way of acquiring phase lock of a phase-locked loop onto a noisy signal from an initially unlocked state. The method uses a quadrature detector, freezing the phase feedback quadrature signal component when the other quadrature signal component is negative. The portion of Fig. 1 above the dotted line illustrates a conventional phase-locked loop (PLL). The present technique adds the elements below the dotted line which are a second multiplier operating with the reference signal delayed 90OE, and a zero-order hold which freezes the output of the first multiplier when the output of the second multiplier is negative. The second multiplier yields the other of the two outputs of what is called a "quadrature demodulator". The two outputs provide effective "real" and "imaginary" signals. Because the second multiplier acts in phase with a locked signal, its output is a "synchronous demodulation". The top multiplier, (s+1)/s integrator block, and voltage-controlled oscillator (VCO) with a 1/s transfer function, together would form a conventional PLL. Note that

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which is the sum of a single and double integration. When the output of the added synchronous demodulator goes negative, the added Hold circuit freezes the output of the top multiplier prior to the integration. The effect of this hold function is understood using phasors. When the output of the top and bottom multipliers of Fig. 1 are plotted together, vertical axis for the bottom one and horizontal for the top, a locked signal appears in Fig. 2A, and because the Hold circuit is not activated, lock is maintained as in a conventional system. When these same outputs are plotted for an out-of-lock signal as in Fig. 2B, a circle is seen. With only the elements above the dotted line in Fig. 1, the system would be a conventional phase-locked loop. In that conventional system because of the 1/s term, the rotation is slower, thus spending more time in quadrants I and IV, and because of the 1/s2 term, the rotation slows down in the same quadrants. The system spends more time in quadrants I and IV slowing down than in quadrants II and III speeding up, and, as a result, after each cycle th...