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Encoding Mutually Exclusive PLA Outputs

IP.com Disclosure Number: IPCOM000046810D
Original Publication Date: 1983-Aug-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 2 page(s) / 39K

Publishing Venue

IBM

Related People

Leininger, JC: AUTHOR [+3]

Abstract

The mutually exclusive output lines of a programmable logic array (PLA) are encoded to reduce the number of such output lines, the number of stages in an output register driven by such output lines and the number of inputs to succeeding PLAs coupled to such output register. This enables a reduction in the size of PLAs and registers fabricated on integrated circuit chips. The use of more than one PLA on a semiconductor integrated circuit chip is becoming more common in large-scale integration (LSI) chip designs. Frequently, several outputs of one PLA are mutually exclusive so that only one or a group of outputs is active at any given time. If these outputs are encoded, then fewer outputs from the PLA will be required and the output OR array size of such PLA will be reduced.

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Encoding Mutually Exclusive PLA Outputs

The mutually exclusive output lines of a programmable logic array (PLA) are encoded to reduce the number of such output lines, the number of stages in an output register driven by such output lines and the number of inputs to succeeding PLAs coupled to such output register. This enables a reduction in the size of PLAs and registers fabricated on integrated circuit chips. The use of more than one PLA on a semiconductor integrated circuit chip is becoming more common in large-scale integration (LSI) chip designs. Frequently, several outputs of one PLA are mutually exclusive so that only one or a group of outputs is active at any given time. If these outputs are encoded, then fewer outputs from the PLA will be required and the output OR array size of such PLA will be reduced. If the outputs are latched in an output register, then fewer stages will be required in such register. If the first PLA having the encoded outputs feeds the inputs of a subsequent PLA, then fewer inputs will be required for this subsequent PLA and its AND array will also be reduced in size and will be physically smaller. Size reductions will, therefore, be realized in the first PLA OR array, the output register and the second PLA AND array. The drawing shows a first PLA with its output lines feeding an output register 10. This first PLA (PLA #1) includes an input AND array 11 connected by way of a goodly number of product lines to an output OR array 12. The output lines of register 10 are connected to a second PLA (PLA #2) which is comprised of an input AND array 13 coupled by way of multiple product lines to an output OR array 14. The use of register 10 is optional. If output lines f1 through f6 of the fir...