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Test Pattern Generation for Partitioned Programmable Logic Arrays

IP.com Disclosure Number: IPCOM000046823D
Original Publication Date: 1983-Aug-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 5 page(s) / 44K

Publishing Venue

IBM

Related People

Muhr, JT: AUTHOR [+2]

Abstract

Test pattern generation for either single-bit or double-bit partitioned programmable logic arrays (PLAs) has been accomplished in a similar manner to other combinational circuit test pattern generation. The logic combinations of the AND and OR circuits are first broken down into primitives, normal stuck fault generation is performed, and then fault simulation on the primitives is done. This produces a rather large test pattern set which must be stored in the system and transmitted to the tester. The process is time consuming and requires capability to handle the abundance of data. An alternate technique is to randomly select the test patterns. Unfortunately, these methods do not give 100% detection of PLA failures.

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Test Pattern Generation for Partitioned Programmable Logic Arrays

Test pattern generation for either single-bit or double-bit partitioned programmable logic arrays (PLAs) has been accomplished in a similar manner to other combinational circuit test pattern generation. The logic combinations of the AND and OR circuits are first broken down into primitives, normal stuck fault generation is performed, and then fault simulation on the primitives is done. This produces a rather large test pattern set which must be stored in the system and transmitted to the tester. The process is time consuming and requires capability to handle the abundance of data. An alternate technique is to randomly select the test patterns. Unfortunately, these methods do not give 100% detection of PLA failures. It is possible to generate a personalized test pattern set for either a single-bit or a double-bit partitioned PLA which overcomes such difficulties. This is accomplished by developing a basic set of patterns prior to testing and utilizing these patterns as a basis for a much larger pattern set which is tester expanded from an appropriate one of the basic pattern sets. The basic set of patterns represents each pattern that "makes" a product term. Each individual pattern of the basic set represents a series of tests. A series of tests is comprised of the application of the basic "make" pattern, plus a sequence of "block" patterns associated with the "make" pattern. The "block" sequence is a set of perturbations on the original pattern, with each of the sequences having one and only one bit position flipped to the state opposite that of the original pattern (bit flip). Each series of tests thoroughly tests a product term in "1 + the number of inputs" tests. The total single-bit partitioned PLA will be thoroughly tested in "the number of product terms" times "1 + the number of inputs" tests. The volume of data sent to the tester will be: (total of volume of data applied)

(1 + the number of inputs) Significant test quality can be achieved by the selection of force values for the various "don't care" conditions. This analysis is also done prior to test application. The analysis and initial pattern set generation is as indicated below. 1. Create a pattern set with 0 in the "don't care" positions and 1 or 0 corresponding to the H and L

positions in the product terms. This will be a

"make" pattern set for this PLA. 2. Choose a value for each "don't care" position in each product term such that the value "blocks"

most other product terms (i.e., if a 1 blocks more

product terms than 0 does, put a 1 in those "don't

care" positions). 3. Take each pattern in turn and compare it to all other patterns to determine if that pattern may

"make" some other product term. If no pattern

makes any other product term, the process is

completed. If, however, another is satisfied,

proceed with the following for each pattern that

1

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makes another. 4. For any pattern that m...