Browse Prior Art Database

Multiconfiguration Funnel Circuits

IP.com Disclosure Number: IPCOM000046826D
Original Publication Date: 1983-Aug-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 4 page(s) / 86K

Publishing Venue

IBM

Related People

Andrews, LP: AUTHOR [+3]

Abstract

In the system of Fig. 1, adapter 1 interfaces in various configurations - to pass data in various bit-parallel formats - between I/O channel circuits 2 of a host processing system 3 and a device attachment interface 4. The host system comprises the standard complement of parts including a CPU, a main store and I/O channels. The adapter comprises a microprocessor (MCP), a cycle stealing circuit (CS) having "direct access" to host main storage, and a "flexible funnel" circuit (FF) interfacing between CS and device interface 4. The circuits CS and FF have hardware controls which, after initiation by microprocessor MCP, can operate asynchronously, relative to both the microprocessor and the host CPU, to transfer data between host storage and an attached peripheral device via device attachment interface data bus 6.

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Multiconfiguration Funnel Circuits

In the system of Fig. 1, adapter 1 interfaces in various configurations - to pass data in various bit-parallel formats - between I/O channel circuits 2 of a host processing system 3 and a device attachment interface 4. The host system comprises the standard complement of parts including a CPU, a main store and I/O channels. The adapter comprises a microprocessor (MCP), a cycle stealing circuit (CS) having "direct access" to host main storage, and a "flexible funnel" circuit (FF) interfacing between CS and device interface 4. The circuits CS and FF have hardware controls which, after initiation by microprocessor MCP, can operate asynchronously, relative to both the microprocessor and the host CPU, to transfer data between host storage and an attached peripheral device via device attachment interface data bus 6. The host interface bus 5 is configured for transferring data in 16-bit parallel word units, and the device attachment interface data bus 6 and flexible funnel circuits FF are configurable to interchange data with adapter CS in bit parallel units of 8, 16 or 32 bits. As shown in Fig. 2, circuits FF are also configurable to operate in either unidirectional modes U or bidirectional modes B, and can conduct writing operations W and reading operations R in each mode. In the unidirectional modes, the circuits FF can handle data at the external interface in 8- and 16-bit parallel units (U8 and U16, respectively).

In the bidirectional modes, FF can handle data at the device interface in 16- and 32-bit parallel units. In the unidirectional configurations, write operations are conducted only via the "0" lines of bus 6 and read (input) operations are conducted only via the "1" lines of bus 6. In the 8-bit writing configuration (U8W), only the high-order half of the zero bus (0 high) is used, and in the 8-bit reading configuration (U8R), only the high-order segment of the one bus (1 high) is used. Since the paths used for reading and writing in these unidirectional configurations are relatively exclusive, it will be understood that these configurations can be used to support full duplex communications between an attached device and host storage. In the bidirectional 16-bit modes (B16W and B16R), data is transferred only via the "1" lines of bus 6. In the 32-bit bidirectional configurations (B32W and B32R) the data is passed in 32-bit parallel units over all line elements of bus 6. Consequently, it will be understood that these bidirectional configurations are useful principally for supporting half duplex and simplex forms of communication relative to an attached device. In operation, after preconditioning by microprocessor MCP, circuits CS and FF operate autonomously to conduct the required data transfers. The microprocessor is programmable to initialize CS and FF either through internally stored command programs or in response to commands received one at a time from host system H. Referring to Fig. 3,...