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Browse Prior Art Database

Latch-Up Free CMOS Structure

IP.com Disclosure Number: IPCOM000046831D
Original Publication Date: 1983-Aug-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 2 page(s) / 45K

Publishing Venue

IBM

Related People

Ogura, S: AUTHOR [+3]

Abstract

The following latch-up free CMOS structure utilizes a buried N+ structure to reduce lateral PNP beta and a buried P+ region to reduce lateral NPN beta. The process steps are as follows: The starting substrate material is a highly doped P+ substrate. The region is implanted using an N-well mask, and a P-epi is grown (Fig. 1). Semi-recessed oxide pads are defined by placing an SiO2 layer on the P-epi and forming Si3N4 and poly-Si mesas (Fig. 2) on the SiO2 layer. N-wells are formed by placing negative slope photoresist over the mesa defining the N channel region and ion implanting N impurities into the exposed P-epi (Fig. 3). Polysilicon is deposited over the structure (Fig. 4). The photoresist and its overlying poly-Si are removed and a P implant is made (Fig. 5).

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Latch-Up Free CMOS Structure

The following latch-up free CMOS structure utilizes a buried N+ structure to reduce lateral PNP beta and a buried P+ region to reduce lateral NPN beta. The process steps are as follows: The starting substrate material is a highly doped P+ substrate. The region is implanted using an N-well mask, and a P-epi is grown (Fig. 1). Semi-recessed oxide pads are defined by placing an SiO2 layer on the P-epi and forming Si3N4 and poly-Si mesas (Fig. 2) on the SiO2 layer. N-wells are formed by placing negative slope photoresist over the mesa defining the N channel region and ion implanting N impurities into the exposed P-epi (Fig. 3). Polysilicon is deposited over the structure (Fig. 4). The photoresist and its overlying poly-Si are removed and a P implant is made (Fig. 5). It is optional to form poly sidewalls with poly deposition and P+ field implant. The poly-Si is etched away, and the areas uncovered by Si3N4 are oxidized. This is followed by a conventional CMOS process for producing P- and N- channel devices, as shown in the final device cross-section of Fig. 6.

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