Browse Prior Art Database

High Speed Merged Charge Memory

IP.com Disclosure Number: IPCOM000046833D
Original Publication Date: 1983-Aug-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 2 page(s) / 67K

Publishing Venue

IBM

Related People

Lange, RC: AUTHOR [+2]

Abstract

This is a high density high speed memory array consisting of merged charge memory (MCM) cells. Merged charge memories have been previously described in U.S. Patents 4,040,017 and 4,080,590. In the present arrangement, a cross-sectional view is shown in Fig. 1, while a top view is shown in Fig. 2. Each cell consists of a merged bit line and storage cell, a word line and a word line injector. The advantageous arrangement of having a word line with each injector results in high speed of operation and high storage voltage. The illustrated cell size is 6F2 (where F is the minimum photolithography feature). The operation of this cell is identical to that of a standard one-device random-access memory cell. The details of the read and write operation are best understood by referring to the following table.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 100% of the total text.

Page 1 of 2

High Speed Merged Charge Memory

This is a high density high speed memory array consisting of merged charge memory (MCM) cells. Merged charge memories have been previously described in U.S. Patents 4,040,017 and 4,080,590. In the present arrangement, a cross-sectional view is shown in Fig. 1, while a top view is shown in Fig. 2. Each cell consists of a merged bit line and storage cell, a word line and a word line injector. The advantageous arrangement of having a word line with each injector results in high speed of operation and high storage voltage. The illustrated cell size is 6F2 (where F is the minimum photolithography feature). The operation of this cell is identical to that of a standard one-device random-access memory cell. The details of the read and write operation are best understood by referring to the following table.

(Image Omitted)

Word V V Word line

line bit"0" bit"1" Injector (N+) ________________________________________________________________
_____

Write VH 0 VH VH - VT Store 0 VH VH "

(Storage Node (Storage Node Voltage:2VH-VT) Voltage:VH-VT) Read

VH VH Floating VH Floating " ________________________________________________________________
____

In the foregoing table, VH is a high positive voltage, while VT is the threshold voltage of the devices.

1

Page 2 of 2

2

[This page contains 6 pictures or other non-text objects]