Dismiss
InnovationQ will be updated on Sunday, Oct. 22, from 10am ET - noon. You may experience brief service interruptions during that time.
Browse Prior Art Database

System Master Slice for Fast Turnaround Time

IP.com Disclosure Number: IPCOM000046836D
Original Publication Date: 1983-Aug-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 2 page(s) / 44K

Publishing Venue

IBM

Related People

Logue, JC: AUTHOR [+2]

Abstract

This is an improved microprocessor and an improved technique for fabricating a microprocessor on a semiconductor master slice. As illustrated in the figure this is a personalizable microprocessor on a single semiconductor chip containing not only the microprocessor unit (MPU) but also the peripheral input/output (PIO), a function execution unit (FEU), and a read-only store (ROS) as well as a random-access memory (RAM). A significant aspect of this arrangement is that the FEU and PIO are formed from programmable logic arrays (PLA) for design flexibility at the personalization level. Another important aspect is that the internal bus is common to all elements of the micro processor on the semiconductor master slice (SMS) so that "add on" items are directly pluggable by means of an external bus connected to the internal bus.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 59% of the total text.

Page 1 of 2

System Master Slice for Fast Turnaround Time

This is an improved microprocessor and an improved technique for fabricating a microprocessor on a semiconductor master slice. As illustrated in the figure this is a personalizable microprocessor on a single semiconductor chip containing not only the microprocessor unit (MPU) but also the peripheral input/output (PIO), a function execution unit (FEU), and a read-only store (ROS) as well as a random- access memory (RAM). A significant aspect of this arrangement is that the FEU and PIO are formed from programmable logic arrays (PLA) for design flexibility at the personalization level. Another important aspect is that the internal bus is common to all elements of the micro processor on the semiconductor master slice (SMS) so that "add on" items are directly pluggable by means of an external bus connected to the internal bus. Illustrated attached to the external bus are additional ROS, RAM, and FEUs or PIOs, also constructed from PLAs. In this arrangement, approximately 70% of the chip is constructed from PLAs. For example, the instruction decode and control units as well as the arithmetic logic unit (ALU) are constructed from PLAs. The PLAs are laser alterable, permitting fast turnaround time in the design of a microprocessor. Special purpose microprocessors are readily personalizable by lasering connections in the various PLAs. The registers and RAM require no such special personalization and can be formed by conventiona...