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Accurate Detection of Higher Order Incident Switching in an ON/OFF Chip Wiring Network

IP.com Disclosure Number: IPCOM000046842D
Original Publication Date: 1983-Aug-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 2 page(s) / 34K

Publishing Venue

IBM

Related People

Diepenbrock, J: AUTHOR [+3]

Abstract

A circuit is described for the accurate detection of higher-order incident switching in a fully undisturbed ON/OFF chip wiring network without probing. Single-chip microprocessors are provided with buses on the chip. As these buses constitute a very heavily loaded wiring network for the internal bus drivers, on-chip wiring rules are required. For defining and evaluating these rules, it is very important to detect higher-order incident switching at the receiver input. Detection by probing is not suitable for on-chip buses. Fig. 1 shows the circuit for the accurate detection of higher-order incident switching. Fig. 2 shows the voltage curves at the designated points of the circuit of Fig. 1.

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Accurate Detection of Higher Order Incident Switching in an ON/OFF Chip Wiring Network

A circuit is described for the accurate detection of higher-order incident switching in a fully undisturbed ON/OFF chip wiring network without probing. Single-chip microprocessors are provided with buses on the chip. As these buses constitute a very heavily loaded wiring network for the internal bus drivers, on-chip wiring rules are required. For defining and evaluating these rules, it is very important to detect higher-order incident switching at the receiver input. Detection by probing is not suitable for on-chip buses. Fig. 1 shows the circuit for the accurate detection of higher-order incident switching. Fig. 2 shows the voltage curves at the designated points of the circuit of Fig. 1. The input signal of receiver R1, shown in curve 1, exceeds or drops below its threshold value and is amplified by receiver R1, so that curve 2 is obtained. A flip-flop FF1 and an inverter I1 are connected to the output of receiver R1. The output of flip-flop FF1 is connected, through a driver DR1, to the chip output pad OP1. In addition, the output of flip-flop FF1 is connected to the first input of an AND gate 1, whose second input is linked with inverter I1. The output of AND gate 1 is connected to the setting input of a flip-flop FF2 which, through driver DR2, is connected to another chip output pad OP2. After the input signal has been applied to receiver R1, it is determined at the output...