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NMOS FET Logic

IP.com Disclosure Number: IPCOM000046843D
Original Publication Date: 1983-Aug-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 2 page(s) / 37K

Publishing Venue

IBM

Related People

Haug, W: AUTHOR

Abstract

The reduction of the power supply voltage and the voltage swing significantly improves the power delay product of a logic circuit by means of an additional converter. This leads to an improvement of the design of high-density NMOS FET chips. One of the major problems in the design of VLSI logic chips is power dissipation. The input up-level VIN(UP) applied to a conventional logic block, for example, inverter T5, T6, should be at least VIN'(UP) / VTmax + VODR where VTmax is the maximum threshold voltage of T6 (N 1.5 V) and VODR is the overdrive voltage VGS - VT depending upon the required logic block delay (N N 1.5 V). Therefore, the inverter must be connected to a power supply voltage VL of not less than 3 ... 5 V for generating an output up-level (at T6), guaranteeing that the next logic stage is reliably turned on.

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NMOS FET Logic

The reduction of the power supply voltage and the voltage swing significantly improves the power delay product of a logic circuit by means of an additional converter. This leads to an improvement of the design of high-density NMOS FET chips. One of the major problems in the design of VLSI logic chips is power dissipation. The input up-level VIN(UP) applied to a conventional logic block, for example, inverter T5, T6, should be at least VIN'(UP) / VTmax + VODR where VTmax is the maximum threshold voltage of T6 (N 1.5 V) and VODR is the overdrive voltage VGS - VT depending upon the required logic block delay (N N
1.5 V). Therefore, the inverter must be connected to a power supply voltage VL of not less than 3 ... 5 V for generating an output up-level (at T6), guaranteeing that the next logic stage is reliably turned on. The wide spread of VT, caused by process tolerances, is the main obstacle to a reduced supply voltage VL . The basic idea is to insert a highly sensitive level converter T3, T4 in front of the conventional inverter. The bias network T1, T2 supplies the gate of the level converter input device T4 with the voltage VB N VREF + VT(T2) where VREF is the reference voltage and VT(T2) is the threshold voltage of the diode T2. As the threshold voltages of T2 and T4 cancel each other, the required input up-level VIN(UP) is independent of the threshold voltage VIN(UP) N VREF N 1.5 V and thus can be made much smaller than for a conventional invert...