Browse Prior Art Database

Leakage-Tolerant Sense System

IP.com Disclosure Number: IPCOM000046849D
Original Publication Date: 1983-Aug-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 2 page(s) / 33K

Publishing Venue

IBM

Related People

Arzubi, L: AUTHOR [+3]

Abstract

A sense system is described which permits significant leakage either in a bit line or a sense amplifier without other bit lines breaking down, as is the case with sense schemes currently used in dense memory arrays. In dense memory designs, a highly sensitive means for amplifying small differential signals is the so-called "bucket brigade" sense latch, as illustrated in the figure. All sense latches are connected to a common bus and are set by device T in response to an input signal SET LATCH. The common bus is restored by a bit line pulse RBL, additionally using a bleeder circuit. At the end of the short array cycle, the pulse RBL is cut off to prevent voltage transitions becoming trapped in the bit lines (noise source reducing the raw signal).

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Leakage-Tolerant Sense System

A sense system is described which permits significant leakage either in a bit line or a sense amplifier without other bit lines breaking down, as is the case with sense schemes currently used in dense memory arrays. In dense memory designs, a highly sensitive means for amplifying small differential signals is the so-called "bucket brigade" sense latch, as illustrated in the figure. All sense latches are connected to a common bus and are set by device T in response to an input signal SET LATCH. The common bus is restored by a bit line pulse RBL, additionally using a bleeder circuit. At the end of the short array cycle, the pulse RBL is cut off to prevent voltage transitions becoming trapped in the bit lines (noise source reducing the raw signal). If during the maximum standby time the common bus develops a leakage path, the leakage current is replenished by the bleeder circuit. In this case, the voltage of node C is above the value of voltage VH during the standby time and is cut off just before the sense latch enters the amplification phase. Compared with prior-art devices, this additional circuit, which does not require additional phases, drastically reduces the susceptibility of memory chips to leakages, if a large number of sense latches are dotted.

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