Browse Prior Art Database

Circuit for Input Current Compensation in Restore Circuits of MTL/I2L Semiconductor Storages

IP.com Disclosure Number: IPCOM000046854D
Original Publication Date: 1983-Aug-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 2 page(s) / 50K

Publishing Venue

IBM

Related People

Keinert, J: AUTHOR [+4]

Abstract

A current switch T1, T2 with a current mirror T5, T9, T10, acting as the current source, is used as a restore circuit for MTL/I2L semiconductor storages. In addition to the restore function, this low-resistance output circuit serves to adjust the standby cell current. The input voltage VREF of the restore circuit is generated across several imitated memory cells. These cells, connected in parallel, are traversed by the accurately defined current IBIAS. The load the b-dependent input current IRS of the restore circuit imposes upon the constant current IBIAS, drawn from a suitable current source, influences the magnitude of the current IBIAS in the imitated memory cells.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 57% of the total text.

Page 1 of 2

Circuit for Input Current Compensation in Restore Circuits of MTL/I2L Semiconductor Storages

A current switch T1, T2 with a current mirror T5, T9, T10, acting as the current source, is used as a restore circuit for MTL/I2L semiconductor storages. In addition to the restore function, this low-resistance output circuit serves to adjust the standby cell current. The input voltage VREF of the restore circuit is generated across several imitated memory cells. These cells, connected in parallel, are traversed by the accurately defined current IBIAS. The load the b- dependent input current IRS of the restore circuit imposes upon the constant current IBIAS, drawn from a suitable current source, influences the magnitude of the current IBIAS in the imitated memory cells. The resultant fluctuations in the reference voltage VREF are transferred at a l:l ratio to the voltage VBRL at the bit restore line BRL, connected to the actual memory cells, where they produce a change in the cell current ICELL, whose magnitude in percent is the same as that of the fluctuations of current IBIAS in the imitated memory cells. By means of an additional circuit, the influence of the input current IRS on the cross current IBIAS in the cell reference voltage generator is compensated for almost completely. Thus, VREF is independent of the magnitude of input current IRS, and the fluctuations of cell current ICELL are greatly reduced. For this purpose, an input current compensation circuit compris...