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High Performance Multiple Pu-Shared Scientific Processor Concept

IP.com Disclosure Number: IPCOM000046857D
Original Publication Date: 1983-Aug-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 3 page(s) / 44K

Publishing Venue

IBM

Related People

Blum, A: AUTHOR

Abstract

In multiple processing unit (PU) systems, the PUs may be connected (a) to a shared or non-shared memory subunit through a common single system bus, controlled by a bus arbiter subunit, or (b) directly to a shared memory (dotted lines, Fig. 1). For scientific applications, a floating-point unit (FPU) is provided which is time-shared by more than one PU of the multiprocessor system. It is assumed that the FPU supplies multiple data and status sets (floating-point registers, etc.). The FPU provides sophisticated functions for the fast execution of floating-point instructions. The data and the control and status information for the floating-point operations are transferred to the FPU by the PU which retrieves the result and status data from the FPU after execution of the floating-point instructions.

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High Performance Multiple Pu-Shared Scientific Processor Concept

In multiple processing unit (PU) systems, the PUs may be connected (a) to a shared or non-shared memory subunit through a common single system bus, controlled by a bus arbiter subunit, or (b) directly to a shared memory (dotted lines, Fig. 1). For scientific applications, a floating-point unit (FPU) is provided which is time-shared by more than one PU of the multiprocessor system. It is assumed that the FPU supplies multiple data and status sets (floating-point registers, etc.). The FPU provides sophisticated functions for the fast execution of floating-point instructions. The data and the control and status information for the floating-point operations are transferred to the FPU by the PU which retrieves the result and status data from the FPU after execution of the floating-point instructions. For several PUs sharing one FPU, an arbitration logic is required. PU serialization is effected through request and grant lines. FPU arbitration is necessary if queued floating-point instructions are to be handled and more than one PU request reaches the FPU at the same time. If several PUs share one memory (instruction fetches being serialized in memory either by a system bus or a memory arbiter) and the instruction transfer time from memory through the PU to the FPU is such that PU requests are not simultaneously received by the FPU, no arbitration cycle is required when the FPU is not busy. In this event, the first request received is automatically accepted and processed, whereas subsequent requests have to be queued and require arbitration cycles. However, if at least one of the PUs is connected to a cache or an instruction buffer, instruction fetches or stores address the cache/ buffer directly instead of the memory. In this case, there is no PU serialization in the memory and arbitration is performed for each FPU access, even if the FPU is not busy. In the synchronous transmission mode, the busy condition of the FPU is interlocked by the PU and the FPU clock, so that there is no hazardous switching of the FPU busy condition signal, as the PU and FPU clocks are suitably correlated. In the asynchronous mode, interlocking is performed by providing adequate clocking times in the PU. The PUs and FPU operate in a master-slave relationship, the FPU being the slave and the respective PU the master which communicates with the FPU either directly or, if there is a flush-through connection between memory and FPU, controls the information tran...