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High Speed Latch

IP.com Disclosure Number: IPCOM000046868D
Original Publication Date: 1983-Aug-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 2 page(s) / 34K

Publishing Venue

IBM

Related People

Boyle, DH: AUTHOR

Abstract

The circuit is a two-stage latch made of FET devices. The first stage A includes input devices D4 and D4' and storage circuit devices D1, D2, D3, D5 and D14. The second stage B includes devices D8, D9, D10 and D11. The second stage is connected to the first stage by means of the pair of transfer gates D6 and D7. The output of the second stage is buffered by means of the two devices D12 and D13. The specific circuit feature is the application of opposite polarity signals output from the transfer devices D6 and D7 to the respective gate inputs of D9 and D11 for the pair of cascaded inverters (D8, D9) and (D10, D11). This "push/pull" mode of operation provides a faster signal switching time for the resultant signals applied to the gates of the output buffer portion D12 and D13.

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High Speed Latch

The circuit is a two-stage latch made of FET devices. The first stage A includes input devices D4 and D4' and storage circuit devices D1, D2, D3, D5 and D14. The second stage B includes devices D8, D9, D10 and D11. The second stage is connected to the first stage by means of the pair of transfer gates D6 and D7. The output of the second stage is buffered by means of the two devices D12 and D13. The specific circuit feature is the application of opposite polarity signals output from the transfer devices D6 and D7 to the respective gate inputs of D9 and D11 for the pair of cascaded inverters (D8, D9) and (D10, D11). This "push/pull" mode of operation provides a faster signal switching time for the resultant signals applied to the gates of the output buffer portion D12 and D13. Note that the signal output from the transfer device D6 is immediately applied to the gate D12 of the output buffer circuit and the signal output from the transfer device D7 is also immediately and simultaneously applied to the gate of the device D13 of the output buffer circuit. Thus, it is seen that the output for the overall circuit at the node L2 is immediately effective when signals are passed by the transfer devices D6 and D7, the second stage latch latching these signals.

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