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Design for Self-Test SRL Implementation

IP.com Disclosure Number: IPCOM000046876D
Original Publication Date: 1983-Aug-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 2 page(s) / 42K

Publishing Venue

IBM

Related People

Calvin, DA: AUTHOR

Abstract

This structure combines both signature compressor and pseudo-random generators in each SRL (shift register latch) string using standard L3 latches. The only additional circuitry required is Exclusive-OR (XOR) gates between SRL stages which provide the compression function (Fig. 1). In principle, each L3 latch is used to hold the vector results, while the L2 latch holds the seed of the current vector. These two are Exclusive-ORed together to produce the new vector. The first SRL stage on each chip is driven by the XOR of the feedbacks Fig. 3). (Note: Restricting feedback circuitry to the chip level obviates the use of substrate wiring and chip I/O's to accomplish this on a larger scale.) The test operation begins by initializing the SRL string(s) in the following manner.

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Design for Self-Test SRL Implementation

This structure combines both signature compressor and pseudo-random generators in each SRL (shift register latch) string using standard L3 latches. The only additional circuitry required is Exclusive-OR (XOR) gates between SRL stages which provide the compression function (Fig. 1). In principle, each L3 latch is used to hold the vector results, while the L2 latch holds the seed of the current vector. These two are Exclusive-ORed together to produce the new vector. The first SRL stage on each chip is driven by the XOR of the feedbacks Fig. 3). (Note: Restricting feedback circuitry to the chip level obviates the use of substrate wiring and chip I/O's to accomplish this on a larger scale.) The test operation begins by initializing the SRL string(s) in the following manner. Set "Test Mode" off, hold SRL input at 0 and apply the clock sequence "A, P, B, A, P, B..." until the string is full (all latches set to zero). Testing begins by turning "Test Mode" on, thus connecting the feedback paths and isolating the chip signature collectors. Now, for every "A, B, MC, P" clock sequence one test vector has been generated and the results captured and compressed. When the last vector has been applied and its results captured, the string is scanned out by turning "Test Mode" off, then applying an "A, B, A, B, ..." clock sequence. The L3 contents of each stage (which comprise the final vector results) will cause inversions to occur wherever...