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Failing Field Replaceable Unit Identification in a System Using Signature Analysis

IP.com Disclosure Number: IPCOM000046886D
Original Publication Date: 1983-Aug-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 2 page(s) / 41K

Publishing Venue

IBM

Related People

Tendolkar, NN: AUTHOR

Abstract

Shift register latches (SRLs) on a module are grouped into equivalence classes such that each SRL belonging to the equivalence class Cj implicates the set of field replaceable units (FRUs) contained in set Sj . A FRU is implicated by an SRL if and only if there is some hardware common between the FRU and the domain of the SRL. Since the FRUs implicated by an SRL are known, we know uniquely which class Cj the SRL belongs to. Suppose there are K equivalence classes. For isolating a fault using signature analysis, there should be K signature registers - one signature register for each class Cj . Signature register Rj, 1 < j < K, is fed by SRLs in class Cj . Fig. 1 shows a system which contains 15 modules on 2 boards. A processor controller controls the application of tests and collection of signatures.

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Failing Field Replaceable Unit Identification in a System Using Signature Analysis

Shift register latches (SRLs) on a module are grouped into equivalence classes such that each SRL belonging to the equivalence class Cj implicates the set of field replaceable units (FRUs) contained in set Sj . A FRU is implicated by an SRL if and only if there is some hardware common between the FRU and the domain of the SRL. Since the FRUs implicated by an SRL are known, we know uniquely which class Cj the SRL belongs to. Suppose there are K equivalence classes. For isolating a fault using signature analysis, there should be K signature registers - one signature register for each class Cj . Signature register Rj, 1 < j < K, is fed by SRLs in class Cj . Fig. 1 shows a system which contains 15 modules on 2 boards. A processor controller controls the application of tests and collection of signatures. Expected signatures are stored on the disc. In Fig. 2, a module that contains 3 signature registers is shown. These registers are made up of LSSD (Level Sensitive Scan Design) SRLs. The processor controller can scan the contents of these registers out to determine the signature. In this case the SRLs are divided into 3 classes. SRLs that feed register A implicate module M1. SRLs that feed register B implicate modules M1 and M2 and the board B1. SRLs that feed register C implicate modules M1 and M3 and the board B1. Three expected signatures are required for module M1. If at the end of a...