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Merged Nonvolatile Random-Access Memory Cell

IP.com Disclosure Number: IPCOM000046890D
Original Publication Date: 1983-Aug-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 4 page(s) / 40K

Publishing Venue

IBM

Related People

Cranford, HC: AUTHOR [+2]

Abstract

A major problem with increasing density of single silicon chip nonvolatile random-access memories is that the drive to higher density circuits increases the time required to alter the state of the nonvolatile element when compared to acceptable read/write times. Secondly, the number of store and erase cycles becomes limited. A dual-cell nonvolatile random-access memory approach has been used heretofore in which a fast read/write volatile cell is combined with a nonvolatile cell. Transfer from the volatile cell to the nonvolatile cell is made only when power is removed in this approach. It effectively puts two cells at each memory location in a matrix and thereby results in a decrease in the achievable density as compared to densities of a volatile random-access memory.

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Merged Nonvolatile Random-Access Memory Cell

A major problem with increasing density of single silicon chip nonvolatile random-access memories is that the drive to higher density circuits increases the time required to alter the state of the nonvolatile element when compared to acceptable read/write times.

Secondly, the number of store and erase cycles becomes limited. A dual-cell nonvolatile random-access memory approach has been used heretofore in which a fast read/write volatile cell is combined with a nonvolatile cell. Transfer from the volatile cell to the nonvolatile cell is made only when power is removed in this approach.

It effectively puts two cells at each memory location in a matrix and thereby results in a decrease in the achievable density as compared to densities of a volatile random-access memory. An approach previously taken has been the combining of volatile and nonvolatile cells using both the metal nitride oxide semiconductor and floating gate technologies. The present description deals with floating gate technology because of its use of capacitive coupling elements. Proposals have been made heretofore for using the floating gate as a nonvolatile element and combining it with a volatile static random-access memory. (See Kline, et al., in the article entitled, "Five Volt Only Non-Volatile RAM Owes it all to Polysilicon,"

Electronics, Oct. 11, 1979, page 111, or Wallace in the article entitled, "Electrically Erasable Memory Behaves Like a Fast Nonvolatile RAM," Electronics, May 10, 1979, page 128.) In order to improve achievable density of the dual-cell nonvolatile RAM (random-access memory), the volatile static portion of the dual cell has been replaced by a dynamic RAM cell to solve the density problem.

However, this introduces a new set of problems since the signals to be sensed in dense dynamic RAM are extremely small and a sensitivity to leakage and/or stray coupling effects may occur. (See Burnhart, "The 64-K Bit RAM Teaches a VLSI Lesson," IEEE Spectrum, June 1981, pages 38-42.) The present description of a merged nonvolatile RAM gives a way of achieving improved density over the approach of static plus nonvolatile cell and still allows for greatly improved design margins over the dynamic plus nonvolatile cell approaches. Jiang, et al., ("A 32-K Static RAM Utilizing a Three Transistor Cell," Digest of Technical Papers, IEEE, ISSCC, 1981, pages 86-87) have given a design for improving the density of static RAM and maintaining good design margins. The cell described in Fig. 1 herein modifies the cell of Jiang, et al, by introducing two capacitors and a new insulator material known as a dual electron injector structure material. This material has been described by DiMaria, et al., in "Electrically Alterable Memory Using a Dual Electron Injector Structure," IEEE Electron Device Letters, September 1980, page 179. This new insulator material is used to form the dielectric of one of the capacitors in the presentl...