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Terminal Having ROS/RAM on Feature Cards

IP.com Disclosure Number: IPCOM000046892D
Original Publication Date: 1983-Aug-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 3 page(s) / 74K

Publishing Venue

IBM

Related People

Orr, MA: AUTHOR

Abstract

This article describes a terminal architecture in which the read-only store (ROS) and/or random-access memory (RAM) required to support a particular feature is mounted on the feature card. The addresses which are assigned to RAM/ROS blocks on a feature card permit those blocks to be addressed through an external address bus as if they were part of the base memory. In effect, physically-distributed memory blocks are logically treated as if all were mounted on a single base card. Referring to Fig. 1, many small terminals include a minimum or base microprocessor card 10. The base microprocessor card may interface with external device features (displays, scanners, etc.) through one or more feature cards 12A, 12B, 12C, etc.

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Terminal Having ROS/RAM on Feature Cards

This article describes a terminal architecture in which the read-only store (ROS) and/or random-access memory (RAM) required to support a particular feature is mounted on the feature card. The addresses which are assigned to RAM/ROS blocks on a feature card permit those blocks to be addressed through an external address bus as if they were part of the base memory. In effect, physically- distributed memory blocks are logically treated as if all were mounted on a single base card. Referring to Fig. 1, many small terminals include a minimum or base microprocessor card 10. The base microprocessor card may interface with external device features (displays, scanners, etc.) through one or more feature cards 12A, 12B, 12C, etc. In conventional systems, the ROS or RAM required to support the operation of the attachments would be included on the base card 10. This article proposes that any ROS or RAM required to support a particular device be mounted on the feature card which provides the electrical interface to that device. Specifically, card 12A is shown as having a ROS module only, while cards 12B and 12C are shown as having both ROS and RAM. The feature ROS or RAM would be addressed through an external address bus 14 which can be considered an extension of the address bus used to access the ROS or RAM on the base card 10. Access to the feature ROS/RAM is in each case through a Memory Decode Module (MDM) which will be described in more detail later. To simplify the memory addressing requirements and to permit the feature ROS/RAM to be treated as if it were logically part of the base ROS/RAM, the memory addressing scheme shown schematically in Fig. 2 may be used. In that figure, the abbreviations F1, F2, F3 refer to feature cards 1, 2, and 3, respectively. ROS memory blocks are of uniform size, e.g., one kilobyte blocks. RAM memory blocks are also uniform in size, e.g., two kilobyte blocks. Feature ROS memory blocks are assigned low hexadecimal addresses, such as 0000- 3FFF. RAM addresses might range from 4000 to 4...