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Browse Prior Art Database

Electronic Diskette Unit

IP.com Disclosure Number: IPCOM000046986D
Original Publication Date: 1983-Sep-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 3 page(s) / 53K

Publishing Venue

IBM

Related People

Baker, ED: AUTHOR [+2]

Abstract

A non-mechanical electronic diskette unit 10 is described which may be used as a direct replacement for a floppy disk-type magnetic diskette unit with minimal software changes in a host processor 11. The electronic diskette unit 10 is coupled to the host processor I/O channel bus in the same manner as other I/O devices 12. As far as the host processor 11 is concerned, the electronic diskette unit 10 behaves the same as the traditional mechanical-type floppy disk unit. The electronic diskette unit 10, however, has a much faster operating speed than does the mechanical-type floppy disk unit.

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Electronic Diskette Unit

A non-mechanical electronic diskette unit 10 is described which may be used as a direct replacement for a floppy disk-type magnetic diskette unit with minimal software changes in a host processor 11.

The electronic diskette unit 10 is coupled to the host processor I/O channel bus in the same manner as other I/O devices 12. As far as the host processor 11 is concerned, the electronic diskette unit 10 behaves the same as the traditional mechanical-type floppy disk unit.

The electronic diskette unit 10, however, has a much faster operating speed than does the mechanical-type floppy disk unit. For sake of example, the host processor 11 is assumed to be an IBM Series/1-type processor, and the typical operations described herein for the electronic diskette unit 10 will be in accordance with the requirements of the Series/1 architecture. The electronic diskette unit 10 uses a random-access memory (RAM) storage unit 13 in place of the traditional floppy disk magnetic medium. Data is transferred between the host processor 11 and this RAM storage 13 by way of the processor I/O channel bus, a data register 14 and a microprocessor bus 15. These data transfers are performed in a cycle steal mode relative to the main storage 16 of the host processor 11. The main storage address is supplied to the processor 11 by a cycle steal address register 17, while the RAM storage address is supplied to the RAM storage 13 by a RAM address counter 18. A cycle steal address counter 19 is incremented, and the updated main storage address is loaded into the cycle steal address register 17 for each byte of data transferred to or from the main storage 16. A microprocessor 20 operates in accordance with a microcode control program resident in a control storage unit 21 to supervise the operation of and to control the movement of data, addresses and the like between the various units contained in the electronic diskette unit 10. A byte counter 22 keeps track of the number of data bytes that have been transferred and signals the microprocessor 20 when all the bytes in a diskette sector have been transferred. Depending on the particular diskette format being used, a diskette sector may include 128, 256, 512 or 1024 bytes of data. For any given diskette read or diskette write operation, a complete sector is transferred from or to the diskette unit, as the case may be. At the beginning of each diskette read or diskette write operation, an eight-word device control block is transferred from the host processor 11 to the electronic diskette unit 10 and stored in the control storage 21. Among other things, this device control block includes the following diskette parameters: cylinder number, head number, sector number, sector size and an indication of whether or not double dense recording is being used.

This device control block also includes the main storage 16 starting address and the byte count for the data transfer. The main storage starting add...