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Disable Circuit for RAM Refresh Timer

IP.com Disclosure Number: IPCOM000047009D
Original Publication Date: 1983-Sep-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 2 page(s) / 27K

Publishing Venue

IBM

Related People

Norgren, KS: AUTHOR

Abstract

This article describes a circuit for disabling the internal refresh timer of a dynamic random-access memory (RAM) controller without using a special purpose "disable timer" program pin. Dynamic RAM requires periodic refresh cycles to retain stored data. These refresh cycles are normally requested by a timer internal to a RAM controller. Since, however, memory access is prohibited during the refresh cycle, the forced refresh costs the system some part of its total bandwidth. To counteract this factor, most RAM controllers allow an external refresh request when the system is not otherwise using the memory. The external refresh request is applied through a special program pin and resets the timer which then continues to request refresh cycles at its normal rate.

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Disable Circuit for RAM Refresh Timer

This article describes a circuit for disabling the internal refresh timer of a dynamic random-access memory (RAM) controller without using a special purpose "disable timer" program pin. Dynamic RAM requires periodic refresh cycles to retain stored data. These refresh cycles are normally requested by a timer internal to a RAM controller. Since, however, memory access is prohibited during the refresh cycle, the forced refresh costs the system some part of its total bandwidth. To counteract this factor, most RAM controllers allow an external refresh request when the system is not otherwise using the memory. The external refresh request is applied through a special program pin and resets the timer which then continues to request refresh cycles at its normal rate. The figure shows a circuit which disables the internal timer so that all refresh cycles must occur through external application. In this manner, a maximum of transparent refresh cycles may be utilized in a given application. The circuit is reset when the reset signal 10 pulses active, enabling the internal timer which commences to request refresh cycles at its normal periodic rate. When the system first activates the external refresh request signal, latch 11 is set, preventing any further refresh request signals from the timer. All refresh cycles must be initiated through line
12. This condition remains until the circuit is again reset by the reset signal 10. This circui...