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Use of Multiple Test Processors in an Integrated System

IP.com Disclosure Number: IPCOM000047016D
Original Publication Date: 1983-Sep-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 2 page(s) / 52K

Publishing Venue

IBM

Related People

Grady, A: AUTHOR [+4]

Abstract

Described is a system comprising a plurality of processors, each processor performing a particular test on a DUT (device under test). The architecture to be described has the advantage that test parameter changes can be easily made, as can control parameter changes, because of the ability to access the lowest execution level from the control processor. The figure illustrates N+1 processors for performing N tests simultaneously under the control of separate processors. One processor is the control processor which is linked to N auxiliary processors, as shown in the figure. Each processor executes its own monitor program at power-on. The monitor programs for each auxiliary processor are stored in a read-only memory (ROM) associated with the particular auxiliary processor.

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Use of Multiple Test Processors in an Integrated System

Described is a system comprising a plurality of processors, each processor performing a particular test on a DUT (device under test). The architecture to be described has the advantage that test parameter changes can be easily made, as can control parameter changes, because of the ability to access the lowest execution level from the control processor. The figure illustrates N+1 processors for performing N tests simultaneously under the control of separate processors. One processor is the control processor which is linked to N auxiliary processors, as shown in the figure. Each processor executes its own monitor program at power-on. The monitor programs for each auxiliary processor are stored in a read-only memory (ROM) associated with the particular auxiliary processor. Execution of its monitor program causes each auxiliary processor to configure its environment while the control processor monitors the status of each auxiliary processor via a control bus coupled to its data-in port. When each auxiliary processor is configured, the control processor takes control of the auxiliary processors' address and data buses, creating a substitute bus structure to load program data in the auxiliary processors' read-write memories (RAMs). After loading an auxiliary processor's RAM, the control processor releases the auxiliary processor to execute its tasks, which are also monitored by the control processor over its contr...