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Resistors on Multilayer Ceramic Substrates

IP.com Disclosure Number: IPCOM000047041D
Original Publication Date: 1983-Sep-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 2 page(s) / 77K

Publishing Venue

IBM

Related People

Burgess, AC: AUTHOR [+3]

Abstract

With the continuing expansion of multilayer ceramic (MLC) packaging technology into broader applications, it is desirable to integrate passive components with MLC modules. Described herein is a method of adding resistors to MLC substrates. The method uses MLC wiring to connect into the circuit path where desired and run connecting leads to an area on the external module surface that is available for resistive element placement. At the surface the leads are terminated in parallel bars of molybdenum metallurgy, and the resistor is formed by bridging the parallel molybdenum terminating bars with thick or thin film resistive material which may be trimmed, if necessary. Examples of potential wiring configurations are shown in Figs. 1A, 1B, and 1C. Fig.

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Resistors on Multilayer Ceramic Substrates

With the continuing expansion of multilayer ceramic (MLC) packaging technology into broader applications, it is desirable to integrate passive components with MLC modules. Described herein is a method of adding resistors to MLC substrates. The method uses MLC wiring to connect into the circuit path where desired and run connecting leads to an area on the external module surface that is available for resistive element placement. At the surface the leads are terminated in parallel bars of molybdenum metallurgy, and the resistor is formed by bridging the parallel molybdenum terminating bars with thick or thin film resistive material which may be trimmed, if necessary. Examples of potential wiring configurations are shown in Figs. 1A, 1B, and 1C. Fig. 1A shows a resistor 1 bridging parallel molybdenum terminating bars 2 which are connected to vias 3 on the same chip 4. Fig. 1B shows a similar arrangement connected to two chips 5 and 6. Fig. 1C shows a similar arrangement with two chips and being fed from a common voltage source 9. Trim cut 8 may be added to each resistor 1 when needed. These examples show series connections on the top surface of the substrate, but they could also be parallel arrangements on the top or bottom surface. In addition to top and bottom placement, resistors may be placed on the MLC substrate edge by connecting normal MLC wiring from the substrate circuit to a pad located at the edge of the same lay...