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GaAs LDD E-MESFET FOR ULTRA-HIGH SPEED LOGIC

IP.com Disclosure Number: IPCOM000047051D
Original Publication Date: 1983-Sep-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 2 page(s) / 50K

Publishing Venue

IBM

Related People

Codella, CF: AUTHOR [+2]

Abstract

The LDD (lightly doped drain-source) E-MESFET is an improved MESFET design utilizing a self-aligned gate and LDD structure. The improved device cross section is shown in Fig. 1B along with that of a previously published [*] enhancement-mode MESFET 1A. Since the gate is self-aligned, the length of the lightly doped channel is minimized and, thus, so is the series resistance. The shallow source/ drain extensions can be positioned near the gate edge without affecting the enhancement-mode operation significantly due to the light doping. The n+ doped source/drain regions are positioned further away where they will not affect device threshhold voltage and can be doped heavily to insure good ohmic contacts.

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GaAs LDD E-MESFET FOR ULTRA-HIGH SPEED LOGIC

The LDD (lightly doped drain-source) E-MESFET is an improved MESFET design utilizing a self-aligned gate and LDD structure. The improved device cross section is shown in Fig. 1B along with that of a previously published [*] enhancement-mode MESFET 1A. Since the gate is self-aligned, the length of the lightly doped channel is minimized and, thus, so is the series resistance. The shallow source/ drain extensions can be positioned near the gate edge without affecting the enhancement-mode operation significantly due to the light doping. The n+ doped source/drain regions are positioned further away where they will not affect device threshhold voltage and can be doped heavily to insure good ohmic contacts. The double-implanted source/drain also reduces the peak electric field by spreading out the drain depletion region through the n type shallow source drain extension. Thus, breakdown voltage is increased, permitting higher drain voltage and better performance. The smaller peak field also results in higher mobility. Fabrication of the device begins with the forming of the n-channel by epitaxy or ion implantation into a semi-insulating substrate. Next, the Schottky gate metallization (Ti/W, etc.) is deposited and defined lithographically. SiO2 is now chemical vapor deposited (CVD) and reaction ion etched (RIE) leaving a sidewall spacer on either side of the gate (Fig. 2). The self-aligned n implant is now done, defining the s...