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Process to Increase the Inverse Gain of an NPN Transistor

IP.com Disclosure Number: IPCOM000047053D
Original Publication Date: 1983-Sep-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 2 page(s) / 77K

Publishing Venue

IBM

Related People

Bhatia, HS: AUTHOR [+3]

Abstract

When a transistor is operated in the inverse direction, holes are injected into the epitaxial region because of the low epitaxial dopant concentration. These holes essentially lower the injection efficiency of the inverse device. An N+ guard ring is therefore incorporated to increase the injection for an NPN transistor. The process for making such a high inverse gain NPN transistor is as follows: 1. Form the conventional junction isolation structure, as shown in Fig. 1, wherein the N+ subregion 10 and P+ junction isolation region 12 are in substrate 14, and silicon dioxide layer 16 and silicon nitride layer 18 are located upon the substrate surface. 2. Open the base area in the mask 16, 18 and undercut the layer 16. 3. Deposit molybdenum metal 20 and lift off the metal, leaving the Fig. 2 structure. 4.

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Process to Increase the Inverse Gain of an NPN Transistor

When a transistor is operated in the inverse direction, holes are injected into the epitaxial region because of the low epitaxial dopant concentration. These holes essentially lower the injection efficiency of the inverse device. An N+ guard ring is therefore incorporated to increase the injection for an NPN transistor. The process for making such a high inverse gain NPN transistor is as follows: 1. Form the conventional junction isolation structure, as shown in Fig. 1, wherein the N+ subregion 10 and P+ junction isolation region 12 are in substrate 14, and silicon dioxide layer 16 and silicon nitride layer 18 are located upon the substrate surface. 2. Open the base area in the mask 16, 18 and undercut the layer 16. 3. Deposit molybdenum metal 20 and lift off the metal, leaving the Fig. 2 structure.
4. Diffuse or implant phosphorus into the substrate 14 to produce guard ring N+ region 22 (Fig. 3). Remove by etching the metal layer 20. 5. Thermally oxidize the exposed silicon surface including the surface under the undercut region of layer 18 to form silicon dioxide layer 24. 6. Reactive ion etch the silicon dioxide layer 24 except that portion under the undercut region of layer 18. Diffuse to form P type base region 26, as seen in Fig. 4. 7. Grow a 500 ~ silicon dioxide layer 28, and deposit a layer 30 SiO2, Si3N4, or the like, thereover (Fig. 5). 8. Open the emitter and diffuse N type impurities therethro...