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Browse Prior Art Database

Accurate High-Speed Integrator

IP.com Disclosure Number: IPCOM000047056D
Original Publication Date: 1983-Sep-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 2 page(s) / 33K

Publishing Venue

IBM

Related People

Simpson, RA: AUTHOR

Abstract

The integrator disclosed herein eliminates integrator output errors resulting from unequal turn-on and turn-off delays in the analog switch which connects the integrator input signal to the integrator. The integrator output errors are eliminated by adding a delay module and a logic gate between the control pulse input and the analog switch. Fig. 1 illustrates an integrator which exhibits output errors. The integrator includes a well-known operational amplifier integrator having the requisite resistance and capacitance attached thereto. An analog switch controls the integration time of an input signal by means of a control pulse. Output errors occur because the analog switch does not open and close instantaneously but rather exhibits a finite delay.

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Accurate High-Speed Integrator

The integrator disclosed herein eliminates integrator output errors resulting from unequal turn-on and turn-off delays in the analog switch which connects the integrator input signal to the integrator. The integrator output errors are eliminated by adding a delay module and a logic gate between the control pulse input and the analog switch. Fig. 1 illustrates an integrator which exhibits output errors. The integrator includes a well-known operational amplifier integrator having the requisite resistance and capacitance attached thereto. An analog switch controls the integration time of an input signal by means of a control pulse. Output errors occur because the analog switch does not open and close instantaneously but rather exhibits a finite delay. When the turn-on and turn-off delays are unequal, the actual integration time differs from its expected value, resulting in an error. Fig. 2 illustrates an integrator which eliminates output errors resulting from unequal turn-on and turn-off delays in the analog switch. Compared with Fig. 1, the integrator of Fig. 2 adds a delay and a gate. When the turn-on time of the analog switch is longer than the turn-off time, the gate is an OR gate (shown in Fig. 2). Alternatively, when the turn-on time is shorter than the turn-off time, an AND gate is employed. The delay and logic gate circuits lengthen or shorten the control pulse to the analog switch control input to make the actual analog switc...