Browse Prior Art Database

Phase Coding Circuit for Data Transmission System

IP.com Disclosure Number: IPCOM000047068D
Original Publication Date: 1983-Sep-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 2 page(s) / 45K

Publishing Venue

IBM

Related People

Boudon, G: AUTHOR

Abstract

This proposal relates to a phase coding circuit to be used for transmitting serial data bits from one chip to another, wherein the serial data bit stream is converted into two phase-shifted pulse trains which are transmitted in differential mode with coupled transmission lines. As shown in Fig. 1, signals PH1 and PH2 are generated from serial data bit stream D and clock pulses C1 and C2. The phase shift WT between clock pulses C1 and C2 is equal to the delay of clock pulse C1 through one current switch gate (Fig. 2). This delay can be accurately controlled by the value of the referenced voltage VR applied at the current source S.

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Phase Coding Circuit for Data Transmission System

This proposal relates to a phase coding circuit to be used for transmitting serial data bits from one chip to another, wherein the serial data bit stream is converted into two phase-shifted pulse trains which are transmitted in differential mode with coupled transmission lines. As shown in Fig. 1, signals PH1 and PH2 are generated from serial data bit stream D and clock pulses C1 and C2. The phase shift WT between clock pulses C1 and C2 is equal to the delay of clock pulse C1 through one current switch gate (Fig. 2). This delay can be accurately controlled by the value of the referenced voltage VR applied at the current source S. PH1 and PH2 signals are generated in the transmitter chip from C1, C2, D and D according to the truth table: Two equivalent Boolean equations can be derived from the above truth table for each signal, PH1 or PH2: The coding of the serial data consists in coding the phase shift between PH1 and PH2 signals. In the receiver chip, the difference between PH1 and PH2 can be easily detected and used for reconstructing the data. The coding of the data is as follows: PH1 minus PH2 > 0 if the data is "0". PH1 minus PH2 < 0 if the data is "1". This function can be implemented with combinational logic between C1, C2 and the data signal. Fig. 3 shows the implementation of the logic circuits which generate signals PH1 and PH2, with cascode current switches, according to the schemes: These logic circuit...