Browse Prior Art Database

Fully Automated Microcode Generation System

IP.com Disclosure Number: IPCOM000047070D
Original Publication Date: 1983-Sep-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 2 page(s) / 39K

Publishing Venue

IBM

Related People

Antoine, M: AUTHOR [+3]

Abstract

Generation of microcode is time consuming and requires generally specific non-automated tools in order to prepare microcode modules, i.e., programmable read only memory (PROM) modules. The system described, which is used as a tool for an engineering model to be developed, can also be used to create PROM modules in case of microcode modification. The present system uses an information handling system (IHS), say, an IBM System/370, provided with a Direct Communication Feature (DCF), a Channel Addressable Control Unit (CACU) or similar unit, and a display I/O terminal for the microprogrammer, as represented in the figure. This IHS is connected to the system whose part of the microcode sections must be created or modified, say, a Line Switching System (LSS).

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Fully Automated Microcode Generation System

Generation of microcode is time consuming and requires generally specific non- automated tools in order to prepare microcode modules, i.e., programmable read only memory (PROM) modules. The system described, which is used as a tool for an engineering model to be developed, can also be used to create PROM modules in case of microcode modification. The present system uses an information handling system (IHS), say, an IBM System/370, provided with a Direct Communication Feature (DCF), a Channel Addressable Control Unit (CACU) or similar unit, and a display I/O terminal for the microprogrammer, as represented in the figure. This IHS is connected to the system whose part of the microcode sections must be created or modified, say, a Line Switching System (LSS). The LSS comprises a Central Processing Logic (CPL), with a ROS (not shown) containing the microcode in PROM modules) and Storage Facility (STG) which stores the application programs controlling the switching network (SWN) through a native Switching Control Adapter (SCA), and controlling at least a plurality of I/O terminals through a Channel Adapter (CA). The microcode stored in ROS emulates the control program instructions; the execution of a given control program instruction is achieved by the execution of a series of micro instructions. It also controls the I/O bus and drives the SCA and CA hardware, and assumes some service and diagnostics functions. As a development tool, in the early phase of microcode development, the microprocessor hardware in CPL is usually not available and the microcode is developed in simulation mode. Then, when first hardware becomes available, a ROS cannot be used, as microcode is not fully operational, and a random access memory (RAM) with characteristi...