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Timing Recovery Circuit

IP.com Disclosure Number: IPCOM000047071D
Original Publication Date: 1983-Sep-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 2 page(s) / 38K

Publishing Venue

IBM

Related People

Croisier, A: AUTHOR

Abstract

In digital telephone systems where signals are transmitted in bursts of about 10 bits from line attachment modules, the subscriber station needs to recover bit timing for further handling of the digital signals. A known technique for timing recovery is based on start-stop operation. The first bit (start bit) received by the station resets a counter which is driven by a fixed frequency clock. The counter drives a decoder DEC which drives a sampling gate, for the detection of subsequent bits, with the proper phase relative to start bit transition (start pulse). The disadvantage of this technique is that timing error made on the start pulse adds to the timing error of each subsequent bit. Therefore, a costly high speed counter is necessary, typically running at 4 MHz.

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Timing Recovery Circuit

In digital telephone systems where signals are transmitted in bursts of about 10 bits from line attachment modules, the subscriber station needs to recover bit timing for further handling of the digital signals. A known technique for timing recovery is based on start-stop operation. The first bit (start bit) received by the station resets a counter which is driven by a fixed frequency clock. The counter drives a decoder DEC which drives a sampling gate, for the detection of subsequent bits, with the proper phase relative to start bit transition (start pulse). The disadvantage of this technique is that timing error made on the start pulse adds to the timing error of each subsequent bit. Therefore, a costly high speed counter is necessary, typically running at 4 MHz. The suggested circuit uses two clock signals A and B, each of which is a square wave of 1.024 MHz, offset by 244 ns with respect to each other (90-degrees phase offset). By comparing the phase states of the A and B signals, one of the 4 pulse trains obtainable Fig. 1) is selected depending upon the time of sampling by the start pulse. The corresponding circuit (Fig. 2) comprises two latches LA and LB which hold the state of clocks A and B at start pulse time. The states in LA, LB are kept for the whole duration of the 10-bit burst of information transmitted from a Line Interface Subscriber Module to the telephone station. Compare circuit COMP now delivers a 244 ns pulse each tim...